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Show new changes starting from 21:51, 31 December 2025
 
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29 December 2025

     15:21  Abacus Computer‎ diffhist +260‎ Timm talk contribs

27 December 2025

 N    07:12  Memory‎‎ 2 changes history +283‎ [Timm‎ (2×)]
     
07:12 (cur | prev) +4‎ Timm talk contribs
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07:12 (cur | prev) +279‎ Timm talk contribs (Created page with "has: merge(1->2 bit) split (2->1 bit) memory (16bit*256address read only) clock and pulse (rising edge detector) and yes all of it has in digital logic sim (name;bits) Input (;bits,what to output) [name;type;args] NOT gate (a;1) [b;1->8;a] [c;memory;b,1,0] (;1,c) User:Timm")

26 December 2025

N    13:05  AddByte‎ diffhist +226‎ Timm talk contribs (Created page with " A B do A* =+ B* has regs IP R1 RN #ALWAYS CONTAIN NEGATIVE ONE R0 I/O MAX X #OUTPUT X X MAX #X =+ INPUT NOP R0 R0 NOT OP IP A X R1 MAX X AND OP IP A IP R1 X B MAX X IF A = 0 THEN DEC B IP A B RN User:Timm")
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