Memory

has: merge(1->2 bit) split (2->1 bit) memory (16bit*256address read only) clock and pulse (rising edge detector) and yes all of it has in digital logic sim

(name;bits) Input

(;bits,what to output)

[name;type;args]

NOT gate

(a;1) [b;1->8;a] [c;memory;b,1,0] (;1,c)

User:Timm