Teriyaki

This page is a work in progress and is likely to undergo major changes in the future.

Teriyaki is a specification for an esoteric video display processor (VDP) discovered by User:Orby during April of 2017. It has no video RAM and supports one on-screen color.

Introduction

Teriyaki proposes a unique challenge to programmers. Because Teriyaki has no video RAM and only supports a single on-screen color, graphics must be drawn by updating the palette as the beam progresses; the ultimate form of racing the beam. Teriyaki supports a fixed 256x240 resolution. Teriyaki also provides control over a single square wave oscillator for audio output. Teriyaki is expected to run off the same clock as the CPU. The refresh rate and voice frequency are tied to the master clock (MC). Use of Teriyaki is encouraged in esoteric VMs.

Registers

Teriyaki has a two hardware registers; the color palette (CP) and the voice frequency (VF) registers. CP indicates the color that is currently drawn to the screen. VF indicates the frequency of the square wave oscillator for audio output. It is recommended that implementations map registers to main memory.

The width of each register is implementation specific, but must be a multiple of 8. Bit depth variations of Teriyaki may be referred to as n-bit Teriyaki controllers. The recommended value of n is 16. For n = 16, it is recommended that the CP use a 565 format: 5 bits for red intensity, 6 bits for green intensity and 5 bits for blue intensity. It is also recommend that the square wave oscillator frequency be a sixteenth of MC divided by VF or (MC / 16) / VF. For example, if the master clock is running at 30 Mhz and VC = 4261, then the square wave oscillator should produce a tone of approximately 440 Hz. The VF value of 0 has the special property of silencing the voice.

Timing

Teriyaki should run off the same clock as the CPU. I've tried to keep the numbers close to the NTSC standard if a 60 Mhz clock is used. Each refresh lasts 1,000,000 cycles and can be broken down into a VBLANK period, a sequence of CP reads, and an HBLANK interval between scan lines. The refresh rate is dependent upon the system clock. The VBLANK period lasts 88,000 cycles. There are 12 cycles between each CP read during which a pixel is drawn. Finally, each HBLANK interval lasts 728 cycles. Therefore, a 60 Hz refresh would require a 60 Mhz system clock. A more modest machine might use a 30 Hz refresh and a 30 Mhz clock.

I think these numbers aren't horribly far off from NTSC standards and could probably be fudged to meet them. There are 3800 cycles per scan line. With a 60 Mhz clock, that's a horizontal scan rate of 15.78 Khz which seems reasonable (analog televisions are around 15.75 Khz). We also have a 63.3 µs scan line which is close to the NTSC standard of 63.9 µs. The 728 cycle HBLANK comes out to 12.1 µs which drags a little compared to the 10.9 µs NTSC standard. We're skipping 22 of the 262 scan lines in the NTSC standard for the sake of our VBLANK, which is well above the 5% threshold which I believe is the minimum. If you're knowledgeable on this subject (I'm not) and have tips or ideas to contribute, drop me a line.

Interrupts

You don't get any! Better start counting those cycles!

Strategies

A good strategy to program Teriyaki may be to render the frame during the VBLANK, then spend the time between CP reads updating CP according to the frame buffer. Of course you'll have to find a clever strategy to do this because a simple linear frame buffer would only leave 1 cycle per pixel to draw! Scan line effects can be produced by performing certain calculations during the horizontal blanking interval of course, so get those raster bars ready ;)

See also

• A1 a saucy CPU specification to be used with Teriyaki