User:Joaozin003/Developing area

This is where I develop languages before making separate pages for them.

2D Signal-Sending Mini-Processors

Grid

The grid is a cartesian plane with processors/structures on each point.

At the center of the grid, there is the structure called the I/O Request Handler (IORH for short). It handles everything related to I/O.

Scattered around the grid are processors. No two processors can be at the same point in the grid.

Uninteresting 8-bit processor

Address space

$0000-$1EFF RAM
$1F00-$1FCF STK (still RAM, 104 entries)
$1FD0-$1FFF VPL (VRAM pallette)
$2000-$2FFF VCH (VRAM chars)
$3000-$3FFF VCL (VRAM colors)
$4000-$5FFF SRM (can be used as even more RAM sometimes)
$6000-$FFFF ROM (40KB ROM!)

VRAM specs

• User-defined 4-bit pallete (defined at CPAL)
• 32x32 ASCII display
• Each byte of VCL encodes:

BBBBCCCC
* B for background color
* C for char color