User:Alikberov/Koy-Code
Paradigm(s) | imperative |
---|---|
Designed by | Alikberov |
Appeared in | 2019 |
Memory system | flat |
Computational class | Turing complete (Koyaanisqatsi) |
Reference implementation | Koyaanisqatsi |
Dialects | Koy-Code, Koy-Code |
File extension(s) | .koy |
Koyaanisqatsi is an esoteric processor unit invented in 2019 by Alikberov in Logisim program with the goal of being simple and transparent even in machine code. Lots of byte-code is just abbreviation of instructions and dump just represent the machine code like disassembling view. In this case the machine code coming as pseudocode too.
Byte-code overview
So, Code A1 is sign for using register A1 as accumulator, and Code 3D is sign for use register #3 in bitwise Disjunction.
But difficultest region in code table is prefixes, because prefixes can very change logic of instruction.
Machine code | Mnemonic | Description |
---|---|---|
__ AB __ __ | ARG A,B | Use Operands A,B |
__ __ A9 __ | REG A9 | Use Register A9 |
__ __ __ 3D | OR A9,B3 | Bitwise Disjunction A9 and B#3 |
12 __ __ 3D | OR A9,[D1+2],B3 | Bitwise Disjunction Memory cell pointed with prefix [D1+2] and B3 then save result to current accumulator (A9) |
__ __ __ CF | CCF | Complement the CF flag |
12 __ __ CF | JCF D1+2 | Jump to address pointed by prefix D1+2 if flag CF is Fictive |
12 34 __ CE | JCE D1+D3+24 | Jump to address pointed by prefixes D1+D3+24 if flag CF is Enabled |
12 34 56 7C | AND A9,[D1+D3+D5+246],B7 | Bitwise Conjunction Memory cell pointed with prefix [D1+D3+D5+246] and B7 then save result to current accumulator (A9) |
__ __ __ 00 | HLT | Halt program (Jump to 0 and warm restart BIOS, current IP saving to D0-vector) |
BIOS starting code
Sphinx C-- like dialect
void ReBoot(void) { // If D0 is clear (this is a "Cold-Start") - then Jump to 256 #pragma org(0) if( (A9 = B0 | C0) == 0 ) // B0 is alias of D0H - HI(D0) // C0 is alias of D0L - LO(D0) IP = 256; else // Else there was "Warm-Start" by HALT-command at the address pointed in D0 { INT(0xF800); HALT(); } }
Assembly byte-code
_IP_ _Byte-Code_ __Short__Record__ _Classic_Record_ _Standard_Record_ ___Descriptions___ 0000 -- AB -- --|A,B |ARG A,B | ;Define Arguments 0001 -- -- A9 --|A9 |REG A9 | ;Select Register 0002 -- -- -- 0F|FOR 0 |FOR A,B0 |MOV A9,B0 ;For A9 load B0 0003 -- AC -- --|A,C |ARG A,C | ;Redefine Arguments 0004 -- -- -- 0D|DIS 0 |OR A,C0 |OR A9,C0 ;Bitwise Disjunction 0005 02 -- -- --|D0+2 |ptr D0+2 | ;Prefixes for ... 0006 -- 05 -- --|D0+2*10+5 |ptr D0+25 | ;...accumulating ... 0007 -- -- 06 --|D0+(2*10+5)*10+6 |ptr D0+256 | ;...pointers for ... 0008 -- -- -- DF|DF |JDF [D0+256] |JZ [D0+256] ;Jump if Zero 0009 -- -- -- F8|F8 |INT F800 |INT [0xF800] ;Interrupt to F80016 000A -- -- -- 00|\0 |HALT |HLT ;After interruption
Dump of BIOS starting code
ADDR .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F 0000 AB A9 0F AC 0D 02 05 06 DF F8 00 .. .. .. .. .. 0010 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
Few details about Instructions Encoding
ADDR .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F 0000 AB A9 0F AC 0D .. .. .. .. .. .. .. .. .. .. .. /\ /\ /\ /\ /\ || || || || || || || || || \> Read register #0 in translators section (C0) in "Disjunction" instruction || || || || || || || \> Use "C" as right operand (translators now in section "C") || || || || || \> Read register #0 in translators section (B0) in "For" instruction || || || \> Select in section "A" register #9 as accumulator || \> Use "A" as left operand (accumulator) and "B" as right operand (translator)
_IP_ _Byte-Code_ _Standard_Record_ _Analogue_in_C_ 0000 -- AB A9 0F|MOV A9,B0 |A9 = B0 0003 -- AC -- 0D|OR A9,C0 |A9 |= C0 0005 02 05 06 DF|JZ [D0+256] |V = D0 + 256; D0 = IP; IP = DFlag ? V : IP 0009 -- -- -- F8|INT [0xF800] |D0 = IP; IP = 0xF800 000A -- -- -- 00|HLT |D0 = IP; IP = 0x0000 000B 90 90 -- 00|HLT9 |Use Extra Mode #9 in Halting 000E 90 90 -- 00|HLT_ |Just syntax feature ('9' is '_') 0011 80 80 -- 00|HLT0 |Just syntax feature ('8' is '0')
_IP_ ____Byte-Code____|_Standard_Assembler_Mnemonic_ _Descriptions_ 7654 -- -- -- DD D0 6A|ADD D0,D6 |D0 += D6 7657 12 -- -- -- -- 6A|ADD D0,D6,[D1+2] |D0 = D6 + *(WORD *)(D1 + 2) 7659 12 34 -- -- -- 6A|ADD D0,D6,#D1+D3+24 |D0 = D6 + *(WORD *)(D1 + D3 + 24) 765C 10 12 34 -- -- 6A|ADD D0,D6,D1+D3-24 |D0 = D6 + *(WORD *)(D1 + D3 - 24) 7660 10 10 -- -- -- 6A|ADD1 D0,D6 |Use SIMD-Mode #1:x86-PADDQ 7663 20 20 -- -- -- 6A|ADD2 D0,D6 |Use SIMD-Mode #2:x86-PADDD 7666 30 30 -- -- -- 6A|ADD3 D0,D6 |Use SIMD-Mode #3:x86-PADDW 7669 40 40 -- -- -- 6A|ADD4 D0,D6 |Use SIMD-Mode #4:x86-PADDB 766C 80 80 70 70 -- 6A|ADD87 D0,D6 |Use i8087-FPU: FADD ST(0),ST(6) 7671 80 80 70 70 12 6A|ADD D0,87#D1+2,D6 |Use i8087-FPU: FADD DWORD PTR [D1+2] 7677 12 34 56 78 90 0F|LEA D0,[D1+D3+D5+D7+D9+24680]|The i8086-Analogue of LEA
Extra Modes
Extra Modes comes like experimental feature with no concretes. That feature become from instructions decoding mechanism and having no strict ideas about using this. One way is using this for co-processing and memory layering, like variant.
External links
- HABR.com Main basical popular description of conception (Anons / Copyleft) with Demo
- AnyCpu.org Forum discussion
- JsFiddle Just live single Instruction Assembly full Encoder