Instruction Set Architecture

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W32 Titanium (formerly serialized as ua-w32-titanium#nf) is a 32-bit architecture written by User:Alx with native support for data width up to 128 bits, initially written as an extension to D8086, but eventually grew into its own completely separate architecture. Unfortunately, due to it being birthed from a minimal virtualization experiment, it was intended to only index a small subsection of virtual memory, being 2 ** 24 (16777216) bytes, with a predesigned address width of 24 bits, which are not padded to 32 bits in representation either. However, it is still a very powerful (virtual) instruction set architecture. This manual page also speaks in relativity to the standard assembler for this instruction set, when referencing programmable assembly.

The architecture has native support for 8-128 bit dynamic arithmetic computing results for both signed and unsigned operations, and native (through architecture extensions) support for dynamic floating-point arithmetic. Unlike other architectures such as 8086, this architecture does not have complex status flags, and does not combine flags to form GE/LE/GTE/LTE conditions. The following main condition flags in the architecture are (assume unset otherwise):

Flag Mnemonic	Description
OF	Overflow Flag, set if integer arithmetic conditions overflow, (ex. pos + pos leading to a negative result)
SF	Sign Flag, used to determine if an integer arithmetic result has a set sign bit
EF	Equal Flag, set if integer arithmetic result is zero
LF	Less Than Flag, set after integer arithmetic result computes the less-than truthiness of the two operands
GF	Greater Than Flag, set after integer arithmetic result computes the greater-than truthiness of the two operands
LEF	Less Than or Equal To Flag, set after integer arithmetic result computes the less-than or equal-to truthiness of the two operands
GEF	Greater Than or Equal To Flag, set after integer arithmetic result computes the greater-than or equal-to truthiness of the two operands
DF	Debug Flag, used as a trap for certain routines

Register Information

The W32 Titanium architecture contains 62 registers, being...

16 general purpose DWORD-sized registers, notated from GR0-GRF (0-9A-F).
8 general (II) purpose QWORD-sized registers, notated from QR0-QR7.
8 interrupt parameter passing PTRWORD-sized registers, notated from IR0-IR7, also typically used for storing memory addresses.
16 local frame DWORD-sized registers, notated from LR0-LRF, used for passing arguments to subroutines, and as a means to register-allocated non-volatile subroutine variables.
8 stack WORD-sized registers, notated from ST0-ST7, used as fast-read access to stack items, assuming the stack is aligned by WORDs.
1 stack pointer PTRWORD-sized register, which holds the address of the topmost stack item, notated as SPTR.
1 frame pointer PTRWORD-sized register, which is initialized at the same address as the stack pointer, and is used for stack frames, notated as FPTR.
4 Branch-prediction DWORD-sized registers, which are now unused, notated as BR0-BR3.

Stack Information

The stack in the W32 Titanium architecture grows upwards in memory, and is initialized to 0x100000 on startup. Unfortunately due to the address width design choice, the stack becomes unaligned so the STx registers cannot properly index WORD items on the stack.

The stack allows every width to be pushed/popped onto/from, as there are no misalignment issues doing this.

Instruction Operand Notation

Register operands are represented in binary by their mnemonic, matching the encoding number. Register operands take up 1 byte.

Immediate operands are represented in binary with a byteorder of Big Endian. Immediate operands take up either 1, 2, 3, 4, 8, or 16 bytes.

Memory operands are represented in binary with their base, disposition/index (if present) and scale (if present) following. Memory base address operands are always PTRWORD sized if they're an immediate, as well as dispositions/indexes. Scales are always immediates, and with a 7 bit range of unaligned scale.

Operands are solely differentiated by the opcode.

Memory Modes of Operation

The formula for calculating a memory address is: base + (disp * scale) for an incremental address, or base - (disp * scale) for a decremental address.

The legal memory addressal modes are as follows:

       +--------------------------------------+
Md. 0: | BASE: 24 (IMM)                       |
       +--------------------------------------+

Addressal Mode 0 specifies only an immediate base address, with no
disposition or scale, as this address is formed at assemble time.
This addressal mode is suitable for an addressal with an immediate
base, immediate disposition and immediate scale.

Addressal Mode 0 encapsulates the following literal addressals:
 - [imm]
 - [imm+imm]
 - [imm+imm*imm]
 - [imm-imm]
 - [imm-imm*imm]

       +----------------------+--------------------------------------+--------+
Md. 1: | BASE: 8 (REG)        | DISP: 23 (IMM)                       | DIR: 1 |
       +----------------------+--------------------------------------+--------+

Addressal Mode 1 specifies a variable base address, with an immediate disposition.
Since the scale must be immediate in every mode, the <code>disp * scale</code> can
be computed at assemble-time. One bit from the LSB of the disposition is allocated
for the direction of the addressal, to determine whether it is incrementing from the
base address, or decrementing from the base address.

Addressal Mode 1 encapsulates the following literal addressals:
 - [reg]
 - [reg+imm]
 - [reg+imm*imm]
 - [reg-imm]
 - [reg-imm*imm]


       +---------------------------------------+----------------------+----------------+--------+
Md. 2: | BASE: 24 (IMM)                        | DISP: 8 (REG)        | SCALE: 7       | DIR: 1 |
       +---------------------------------------+----------------------+----------------+--------+

Addressal Mode 2 specifies an immediate base address, followed by a variable
disposition. Since this factor cannot be calculated at assemble-time, the
scale is also included, with one bit from the scale allocated to determine
the direction of the addressal.

Addressal Mode 2 encapsulates the following literal addressals:
 - [imm+reg]
 - [imm+reg*imm]
 - [imm-reg]
 - [imm-reg*imm]


       +----------------------+----------------------+----------------+--------+
Md. 3: | BASE: 8 (REG)        | DISP: 8 (REG)        | SCALE: 7       | DIR: 1 |
       +----------------------+----------------------+----------------+--------+

Addressal Mode 3 specifies a variable base address, and a variable
disposition. This factor is also impossible to calculate at assemble
time. The scale allocates one bit for the addressal direction.

Addressal Mode 3 encapsulates the following literal addressals:
 - [reg+reg]
 - [reg+reg*imm]
 - [reg-reg]
 - [imm-reg*imm]

VM Datatype Information

The W32 Titanium architecture's word size is 32 bits, and natively supports the following data widths:


Width (bits)	Notation	Notation Alias	Formula
8	QAWORD (Quarter WORD)	BYTE	WORD / 4
16	HWORD (Half WORD)	WORD86	WORD / 2
24	PTRWORD (Pointer WORD)	N/A	WORD - 8
32	WORD	DWORD86	WORD
64	DWORD (Double WORD)	QWORD86	WORD * 2
128	QWORD (Quad WORD)	OWORD86, XMMWORD86	WORD * 4

Instruction Encodings

The notation used in the following table is as follows:

/o16 ...: 16-bit opcode

/w8: 8 bits of width

/w16: 16 bits of width

/w24: 24 bits of width

/w32: 32 bits of width

/w64: 16 bits of width

/w128: 16 bits of width

/m0: Memory mode 0, 24 bits of data

/m1: Memory mode 1, 32 bits of data

/m2: Memory mode 2, 40 bits of data

...

Instruction encodings for `OR`
Literal	Opcode	Operand 1	Operand 2	Operand 3	Operand 4
`qword, xmmword86 or(q) reg128, reg128`	`/o16 05cd`	`/w8`	`/w8`	`N/A`	`N/A`
`qword, xmmword86 or(q) reg128, imm128`	`/o16 05ce`	`/w8`	`/w128`	`N/A`	`N/A`
`qword, xmmword86 or(q) reg128, [mem128]`	`/o16 05cf`	`/w8`	`/m0`	`N/A`	`N/A`
`qword, xmmword86 or(q) reg128, [mem128]`	`/o16 05d0`	`/w8`	`/m1`	`N/A`	`N/A`
`qword, xmmword86 or(q) reg128, [mem128]`	`/o16 05d1`	`/w8`	`/m2`	`N/A`	`N/A`
`qword, xmmword86 or(q) reg128, [mem128]`	`/o16 05d2`	`/w8`	`/m3`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], reg128`	`/o16 05d3`	`/m0`	`/w8`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], reg128`	`/o16 05d4`	`/m1`	`/w8`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], reg128`	`/o16 05d5`	`/m2`	`/w8`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], reg128`	`/o16 05d6`	`/m3`	`/w8`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], imm128`	`/o16 05d7`	`/m0`	`/w128`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], imm128`	`/o16 05d8`	`/m1`	`/w128`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], imm128`	`/o16 05d9`	`/m2`	`/w128`	`N/A`	`N/A`
`qword, xmmword86 or(q) [mem128], imm128`	`/o16 05da`	`/m3`	`/w128`	`N/A`	`N/A`
`dword, qword86 or(d) reg64, reg64`	`/o16 05db`	`/w8`	`/w8`	`N/A`	`N/A`
`dword, qword86 or(d) reg64, imm64`	`/o16 05dc`	`/w8`	`/w64`	`N/A`	`N/A`
`dword, qword86 or(d) reg64, [mem64]`	`/o16 05dd`	`/w8`	`/m0`	`N/A`	`N/A`
`dword, qword86 or(d) reg64, [mem64]`	`/o16 05de`	`/w8`	`/m1`	`N/A`	`N/A`
`dword, qword86 or(d) reg64, [mem64]`	`/o16 05df`	`/w8`	`/m2`	`N/A`	`N/A`
`dword, qword86 or(d) reg64, [mem64]`	`/o16 05e0`	`/w8`	`/m3`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], reg64`	`/o16 05e1`	`/m0`	`/w8`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], reg64`	`/o16 05e2`	`/m1`	`/w8`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], reg64`	`/o16 05e3`	`/m2`	`/w8`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], reg64`	`/o16 05e4`	`/m3`	`/w8`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], imm64`	`/o16 05e5`	`/m0`	`/w64`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], imm64`	`/o16 05e6`	`/m1`	`/w64`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], imm64`	`/o16 05e7`	`/m2`	`/w64`	`N/A`	`N/A`
`dword, qword86 or(d) [mem64], imm64`	`/o16 05e8`	`/m3`	`/w64`	`N/A`	`N/A`
`word, dword86 or(w) reg32, reg32`	`/o16 05e9`	`/w8`	`/w8`	`N/A`	`N/A`
`word, dword86 or(w) reg32, imm32`	`/o16 05ea`	`/w8`	`/w32`	`N/A`	`N/A`
`word, dword86 or(w) reg32, [mem32]`	`/o16 05eb`	`/w8`	`/m0`	`N/A`	`N/A`
`word, dword86 or(w) reg32, [mem32]`	`/o16 05ec`	`/w8`	`/m1`	`N/A`	`N/A`
`word, dword86 or(w) reg32, [mem32]`	`/o16 05ed`	`/w8`	`/m2`	`N/A`	`N/A`
`word, dword86 or(w) reg32, [mem32]`	`/o16 05ee`	`/w8`	`/m3`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], reg32`	`/o16 05ef`	`/m0`	`/w8`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], reg32`	`/o16 05f0`	`/m1`	`/w8`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], reg32`	`/o16 05f1`	`/m2`	`/w8`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], reg32`	`/o16 05f2`	`/m3`	`/w8`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], imm32`	`/o16 05f3`	`/m0`	`/w32`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], imm32`	`/o16 05f4`	`/m1`	`/w32`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], imm32`	`/o16 05f5`	`/m2`	`/w32`	`N/A`	`N/A`
`word, dword86 or(w) [mem32], imm32`	`/o16 05f6`	`/m3`	`/w32`	`N/A`	`N/A`
`ptrword or(p) reg24, reg24`	`/o16 05f7`	`/w8`	`/w8`	`N/A`	`N/A`
`ptrword or(p) reg24, imm24`	`/o16 05f8`	`/w8`	`/w24`	`N/A`	`N/A`
`ptrword or(p) reg24, [mem24]`	`/o16 05f9`	`/w8`	`/m0`	`N/A`	`N/A`
`ptrword or(p) reg24, [mem24]`	`/o16 05fa`	`/w8`	`/m1`	`N/A`	`N/A`
`ptrword or(p) reg24, [mem24]`	`/o16 05fb`	`/w8`	`/m2`	`N/A`	`N/A`
`ptrword or(p) reg24, [mem24]`	`/o16 05fc`	`/w8`	`/m3`	`N/A`	`N/A`
`ptrword or(p) [mem24], reg24`	`/o16 05fd`	`/m0`	`/w8`	`N/A`	`N/A`
`ptrword or(p) [mem24], reg24`	`/o16 05fe`	`/m1`	`/w8`	`N/A`	`N/A`
`ptrword or(p) [mem24], reg24`	`/o16 05ff`	`/m2`	`/w8`	`N/A`	`N/A`
`ptrword or(p) [mem24], reg24`	`/o16 0600`	`/m3`	`/w8`	`N/A`	`N/A`
`ptrword or(p) [mem24], imm24`	`/o16 0601`	`/m0`	`/w24`	`N/A`	`N/A`
`ptrword or(p) [mem24], imm24`	`/o16 0602`	`/m1`	`/w24`	`N/A`	`N/A`
`ptrword or(p) [mem24], imm24`	`/o16 0603`	`/m2`	`/w24`	`N/A`	`N/A`
`ptrword or(p) [mem24], imm24`	`/o16 0604`	`/m3`	`/w24`	`N/A`	`N/A`
`hword, word86 or(h) reg16, reg16`	`/o16 0605`	`/w8`	`/w8`	`N/A`	`N/A`
`hword, word86 or(h) reg16, imm16`	`/o16 0606`	`/w8`	`/w16`	`N/A`	`N/A`
`hword, word86 or(h) reg16, [mem16]`	`/o16 0607`	`/w8`	`/m0`	`N/A`	`N/A`
`hword, word86 or(h) reg16, [mem16]`	`/o16 0608`	`/w8`	`/m1`	`N/A`	`N/A`
`hword, word86 or(h) reg16, [mem16]`	`/o16 0609`	`/w8`	`/m2`	`N/A`	`N/A`
`hword, word86 or(h) reg16, [mem16]`	`/o16 060a`	`/w8`	`/m3`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], reg16`	`/o16 060b`	`/m0`	`/w8`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], reg16`	`/o16 060c`	`/m1`	`/w8`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], reg16`	`/o16 060d`	`/m2`	`/w8`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], reg16`	`/o16 060e`	`/m3`	`/w8`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], imm16`	`/o16 060f`	`/m0`	`/w16`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], imm16`	`/o16 0610`	`/m1`	`/w16`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], imm16`	`/o16 0611`	`/m2`	`/w16`	`N/A`	`N/A`
`hword, word86 or(h) [mem16], imm16`	`/o16 0612`	`/m3`	`/w16`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) reg8, reg8`	`/o16 0613`	`/w8`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) reg8, imm8`	`/o16 0614`	`/w8`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) reg8, [mem8]`	`/o16 0615`	`/w8`	`/m0`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) reg8, [mem8]`	`/o16 0616`	`/w8`	`/m1`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) reg8, [mem8]`	`/o16 0617`	`/w8`	`/m2`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) reg8, [mem8]`	`/o16 0618`	`/w8`	`/m3`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], reg8`	`/o16 0619`	`/m0`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], reg8`	`/o16 061a`	`/m1`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], reg8`	`/o16 061b`	`/m2`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], reg8`	`/o16 061c`	`/m3`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], imm8`	`/o16 061d`	`/m0`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], imm8`	`/o16 061e`	`/m1`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], imm8`	`/o16 061f`	`/m2`	`/w8`	`N/A`	`N/A`
`qaword, byte, byte86 or(b) [mem8], imm8`	`/o16 0620`	`/m3`	`/w8`	`N/A`	`N/A`