PAC-PI

PAC-PI is a computer based on the Abacus Computer. It acts as a modification on the architecture designed around the constraints of physical implementation. Made namely to formalize the use of instruction addresses, and register addresses when pertaining to the length of an instruction. Note that instructions are loaded into RAM before execution.

Overview

An instruction is composed of two words, a word being some uniform number of bits (this is not the same definition as one used by x86/amd64). The first word in an instruction is a destination address, the second the source address (Note that this restricts addresses to being a single word in length). The unsigned integer pointed to the source address is added to that stored in the destination address. An address is simply a unique unsigned integer denoting one unique machine word.

With these definitions we may present a set of registers and their reference addresses (all negative values are in two's complement):

• addr = -1 --- IP: An address pointing to the current instruction, initialized to zero.
• addr = -2 --- IN: The input bus, storing a word of input from the user.
• addr = -3 --- OT: The output bus, writeonly storing a word of output sent too the user.
• addr = -4 --- RS: A scratch register, initialized to zero.
• addr = -5 --- R0: The zero register, readonly, initialized to zero.
• addr = -6 --- R1: The one register, readonly initialized to one.
• addr = -7 --- RN: The negative register, readonly initialized to negative one.
• addr = -8 --- EX: The exit register, when edited the machine halts.

Writing to a readonly/writeonly value is a NOP.

The assembly, therefore might look like so:

 ADD <addr | label | register> <addr | label | register> : Converts to a two word instruction
 LABEL <name> : Creates a symbol <name> to be used in place of the word which points to the current address
 DATA <*immediate_word> : Instantiates words directly into memory
 NOP : Equivalent to ADD R0 <- R0

Therefore a program taking a boolean value A, and a value initialized to zero B, one may invert A like so:

 ; RS := 8
 ADD RS <- R1
 ADD RS <- RS
 ADD RS <- RS
 ADD RS <- RS

 ; if A then B = 8 else B = 0
 ADD  B <-  A
 ADD  B <-  B
 ADD  B <-  B
 ADD  B <-  B

 ADD IP <-  B
 ; IF B = 0
   ADD  A <- R1
   ADD  B <- RS ; B := 8
   NOP
   ADD IP <-  B
 ; ELSE
   ADD  A <- RN
   NOP
   NOP
   NOP
 ; END
 ; B := 0
 ADD B <- RN
 ADD B <- RN
 ADD B <- RN
 ADD B <- RN
 ADD B <- RN
 ADD B <- RN
 ADD B <- RN
 ADD B <- RN

 ; RS := 0
 ADD RS <- RN
 ADD RS <- RN
 ADD RS <- RN
 ADD RS <- RN
 ADD RS <- RN
 ADD RS <- RN
 ADD RS <- RN
 ADD RS <- RN

Extensions

Here shall be defined those alternate forms of PAC-PI which are only distinct for minor changes.

PAC-PIn

This simply denotes a PAC-PI version with a defined word size, so that if a word is 8 bits the most correct name for the machines architecture is PAC-PI8. All versions of PAC-PI are to have an extension of this form if implemented.

PAC-PIn-VAn

This denotes a PAC-PI version with an address length of n words. For example, if a word is 8 bits and addresses are two words then the correct name would be: PAC-PI8-VA2. Note that this *will* change how algorithms must be implemented, namely that each if statement will require N times the number of words to contain the same instructions. Powers of two are recommended for VA size.

Implementations

A PAC-PI8 emulator by User:LillyHStClaire: [1] (Note that test/assembler.asm is a functional fasmg assembler for PACPI-8).