This is an idea for a very simple single-instruction (OISC) CPU.
- Memory is structured as an array of 32-bit words
- 4 words (128 bits) per instruction. Lets's call these words W1,W2,W3,W4
- One internal 64-bit register R64
- One internal 32-bit register R32
Decoding an instruction
- Read memory word at address pointed to by W1 into top 32 bits of R64
- Read memory word at address pointed to by W2 into bottom 32 bits of R64
- For each N from 0 to 7
- Let X be the value (0..F hex) of nybble #N in W3
- Copy nybble #X in R64 to nybble #N in R32
- Store R32 at memory address pointed to by W2
- Jump to the address pointed to by W4
In other words, two 32-bit words (source and destination) are read from two pointer adresses and combined into a 64-bit word (upper | lower). A 32-bit "scrambling word" is used to pick any 8 nybbles (in any order) out of 16 from the combined 64-bit word and store the scrambled 32-bit word back at the destination address. Then an unconditional jump is performed.
This can be considered an extension of ByteByteJump and similar architectures. Arithmetic and conditional jumps can be performed using tables stored in memory. Unlike ByteByteJump this is a full 32-bit architecture. The nybble scrambling scheme also makes handling of tables much more flexible than BBJ. Whereas BBJ only handles tables with 256 entries per row, NybbleScrambler can have tablerows of size 16, 256, 4096, 65536 and so on, i.e. the only requirement is that they must be a power of 16. Another advantage is that it's very easy to do things like swapping bytes / shorts / nybbles in a word, or copy only certain portions of a source word to the destination word (and to a different nybble position in the destination word), or shift / rotate a whole word left or right by a multiple of 4 bits. These and other "nybble tricks" can be performed in a single instruction.