Mach

Mach is a series of virtual machines specified in this page. Currently, there's no implementation to any of them.

Numerical bases and data types

Mach isn't restricted to use binary for storing data. It can use any base described here (as long as the base is a positive integer greater than 1).

Base 2 (binary)

Binary data types used in this page are described in this section. Unsigned integers:

• B2-U8: 8 bits.
• B2-U16: 16 bits.
• B2-U24: 24 bits.
• B2-U32: 32 bits.
• B2-U40: 40 bits.
• B2-U48: 48 bits.
• B2-U56: 56 bits.
• B2-U64: 64 bits.

Big-endian is used and memory is divided into 8-bit parts (commonly called bytes). Also, bit is the common term for a single binary digit. Signed integers (two's complement):

• B2-I8: 8 bits.
• B2-I16: 16 bits.
• B2-I24: 24 bits.
• B2-I32: 32 bits.
• B2-I40: 40 bits.
• B2-I48: 48 bits.
• B2-I56: 56 bits.
• B2-I64: 64 bits.

Memory addresses have the type B2-U32.

Base 3 (ternary)

Ternary data types used in this page are described in this section. Unsigned integers:

• B3-U5: 5 digits.
• B3-U10: 10 digits.
• B3-U15: 15 digits.
• B3-U20: 20 digits.
• B3-U25: 25 digits.
• B3-U30: 30 digits.
• B3-U35: 35 digits.
• B3-U40: 40 digits.

Big-endian is used and memory is divided into 5-digit parts. Signed integers follow an specific format:

• If unsig < 3^N/2, number = unsig, where unsig is the unsigned interpretation of the number and N is the number of digits.
• Else, number = unsig - 3^N.

Signed integer types:

• B3-I5: 5 digits.
• B3-I10: 10 digits.
• B3-I15: 15 digits.
• B3-I20: 20 digits.
• B3-I25: 25 digits.
• B3-I30: 30 digits.
• B3-I35: 35 digits.
• B3-I40: 40 digits.

Memory addresses have the type B3-U20.

Base 5 (quinary)

Quinary data types used in this page are described in this section. Unsigned integers.

• B5-U4: 4 digits.
• B5-U8: 8 digits.
• B5-U12: 12 digits.
• B5-U16: 16 digits.
• B5-U20: 20 digits.
• B5-U24: 24 digits.
• B5-U28: 28 digits.
• B5-U32: 32 digits.

Big-endian is used and memory is divided into 4-digit parts. Signed integers follow an specific format:

• If unsig < 5^N/2, number = unsig, where unsig is the unsigned interpretation of the number and N is the number of digits.
• Else, number = unsig - 5^N.

Signed integer types:

• B5-I4: 4 digits.
• B5-I8: 8 digits.
• B5-I12: 12 digits.
• B5-I16: 16 digits.
• B5-I20: 20 digits.
• B5-I24: 24 digits.
• B5-I28: 28 digits.
• B5-I32: 32 digits.

Memory addresses have the type B5-U16.

Generalised data types

• U1: B2-U8, B3-U5, B5-U4.
• U2: B2-U16, B3-U10, B5-U8.
• U3: B2-U24, B3-U15, B5-U12.
• U4: B2-U32, B3-U20, B5-U16.
• U5: B2-U40, B3-U25, B5-U20.
• U6: B2-U48, B3-U30, B5-U24.
• U7: B2-U56, B3-U35, B5-U28.
• U8: B2-U64, B3-U40, B5-U32.

• I1: B2-I8, B3-I5, B5-I4.
• I2: B2-I16, B3-I10, B5-I8.
• I3: B2-I24, B3-I15, B5-I12.
• I4: B2-I32, B3-I20, B5-I16.
• I5: B2-I40, B3-I25, B5-I20.
• I6: B2-I48, B3-I30, B5-I24.
• I7: B2-I56, B3-I35, B5-I28.
• I8: B2-I64, B3-I40, B5-I32.

Registers

The default value of all registers is 0.

• ra1: U1/I1 (first operand)
• rb1: U1/I1 (second operand)
• rc1: U1/I1 (result)
• ra2: U2/I2 (first operand)
• rb2: U2/I2 (second operand)
• rc2: U2/I2 (result)
• ra3: U3/I3 (first operand)
• rb3: U3/I3 (second operand)
• rc3: U3/I3 (result)
• ra4: U4/I4 (first operand)
• rb4: U4/I4 (second operand)
• rc4: U4/I4 (result)
• ra5: U5/I5 (first operand)
• rb5: U5/I5 (second operand)
• rc5: U5/I5 (result)
• ra6: U6/I6 (first operand)
• rb6: U6/I6 (second operand)
• rc6: U6/I6 (result)
• ra7: U7/I7 (first operand)
• rb7: U7/I7 (second operand)
• rc7: U7/I7 (result)
• ra8: U8/I8 (first operand)
• rb8: U8/I8 (second operand)
• rc8: U8/I8 (result)
• mode: U1 (covered later)

Memory layout

There are two, separated blocks of memory. The first one is where instructions and data live. The other one is where the stack lives. The stack pointer is not accessible to the user and that's why it's not listed there.

Instructions

The value of the mode register defines which set of instructions is being used. Changing its value affects how the next instructions will be interpreted. All instructions are encoded as an U1 (opcode) followed by an U4 (memory operand, may be unused). Any invalid instruction is equivalent to halt.

Mode 0

• halt (opcode 0): terminates the execution of the program.
• setmode1 (opcode 1): sets mode to 1
• setmode2 (opcode 2): sets mode to 2

Mode 1

• setmode0 (opcode 0): sets mode to 0
• mova1 (opcode 1): moves from memory to ra1
• movb1 (opcode 2): moves from memory to rb1
• movc1 (opcode 3): moves from memory to rc1
• mova2 (opcode 4): moves from memory to ra2
• movb2 (opcode 5): moves from memory to rb2
• movc2 (opcode 6): moves from memory to rc2
• mova3 (opcode 7): moves from memory to ra3
• movb3 (opcode 8): moves from memory to rb3
• movc3 (opcode 9): moves from memory to rc3
• mova4 (opcode 10): moves from memory to ra4
• movb4 (opcode 11): moves from memory to rb4
• movc4 (opcode 12): moves from memory to rc4
• mova5 (opcode 13): moves from memory to ra5
• movb5 (opcode 14): moves from memory to rb5
• movc5 (opcode 15): moves from memory to rc5
• mova6 (opcode 16): moves from memory to ra6
• movb6 (opcode 17): moves from memory to rb6
• movc6 (opcode 18): moves from memory to rc6
• mova7 (opcode 19): moves from memory to ra7
• movb7 (opcode 20): moves from memory to rb7
• movc7 (opcode 21): moves from memory to rc7
• mova8 (opcode 22): moves from memory to ra8
• movb8 (opcode 23): moves from memory to rb8
• movc8 (opcode 24): moves from memory to rc8
• umova1 (opcode 25): moves from ra1 to memory
• umovb1 (opcode 26): moves from rb1 to memory
• umovc1 (opcode 27): moves from rc1 to memory
• umova2 (opcode 28): moves from ra2 to memory
• umovb2 (opcode 29): moves from rb2 to memory
• umovc2 (opcode 30): moves from rc2 to memory
• umova3 (opcode 31): moves from ra3 to memory
• umovb3 (opcode 32): moves from rb3 to memory
• umovc3 (opcode 33): moves from rc3 to memory
• umova4 (opcode 34): moves from ra4 to memory
• umovb4 (opcode 35): moves from rb4 to memory
• umovc4 (opcode 36): moves from rc4 to memory
• umova5 (opcode 37): moves from ra5 to memory
• umovb5 (opcode 38): moves from rb5 to memory
• umovc5 (opcode 39): moves from rc5 to memory
• umova6 (opcode 40): moves from ra6 to memory
• umovb6 (opcode 41): moves from rb6 to memory
• umovc6 (opcode 42): moves from rc6 to memory
• umova7 (opcode 43): moves from ra7 to memory
• umovb7 (opcode 44): moves from rb7 to memory
• umovc7 (opcode 45): moves from rc7 to memory
• umova8 (opcode 46): moves from ra8 to memory
• umovb8 (opcode 47): moves from rb8 to memory
• umovc8 (opcode 48): moves from rc8 to memory

Mode 2

• setmode0 (opcode 0): sets mode to 0
• add1 (opcode 1): adds ra1 to rb1 and stores result in rc1 (unsigned)
• add2 (opcode 2): adds ra2 to rb2 and stores result in rc2 (unsigned)
• add3 (opcode 3): adds ra3 to rb3 and stores result in rc3 (unsigned)
• add4 (opcode 4): adds ra4 to rb4 and stores result in rc4 (unsigned)
• add5 (opcode 5): adds ra5 to rb5 and stores result in rc5 (unsigned)
• add6 (opcode 6): adds ra6 to rb6 and stores result in rc6 (unsigned)
• add7 (opcode 7): adds ra7 to rb7 and stores result in rc7 (unsigned)
• add8 (opcode 8): adds ra8 to rb8 and stores result in rc8 (unsigned)
• sadd1 (opcode 9): adds ra1 to rb1 and stores result in rc1 (signed)
• sadd2 (opcode 10): adds ra2 to rb2 and stores result in rc2 (signed)
• sadd3 (opcode 11): adds ra3 to rb3 and stores result in rc3 (signed)
• sadd4 (opcode 12): adds ra4 to rb4 and stores result in rc4 (signed)
• sadd5 (opcode 13): adds ra5 to rb5 and stores result in rc5 (signed)
• sadd6 (opcode 14): adds ra6 to rb6 and stores result in rc6 (signed)
• sadd7 (opcode 15): adds ra7 to rb7 and stores result in rc7 (signed)
• sadd8 (opcode 16): adds ra8 to rb8 and stores result in rc8 (signed)
• sub1 (opcode 17): rc1 = ra1 - rb1 (unsigned)
• sub2 (opcode 18): rc2 = ra2 - rb2 (unsigned)
• sub3 (opcode 19): rc3 = ra3 - rb3 (unsigned)
• sub4 (opcode 20): rc4 = ra4 - rb4 (unsigned)
• sub5 (opcode 21): rc5 = ra5 - rb5 (unsigned)
• sub6 (opcode 22): rc6 = ra6 - rb6 (unsigned)
• sub7 (opcode 23): rc7 = ra7 - rb7 (unsigned)
• sub8 (opcode 24): rc8 = ra8 - rb8 (unsigned)
• ssub1 (opcode 25): rc1 = ra1 - rb1 (signed)
• ssub2 (opcode 26): rc2 = ra2 - rb2 (signed)
• ssub3 (opcode 27): rc3 = ra3 - rb3 (signed)
• ssub4 (opcode 28): rc4 = ra4 - rb4 (signed)
• ssub5 (opcode 29): rc5 = ra5 - rb5 (signed)
• ssub6 (opcode 30): rc6 = ra6 - rb6 (signed)
• ssub7 (opcode 31): rc7 = ra7 - rb7 (signed)
• ssub8 (opcode 32): rc8 = ra8 - rb8 (signed)
• mul1 (opcode 33): rc1 = ra1 * rb1 (unsigned)
• mul2 (opcode 34): rc2 = ra2 * rb2 (unsigned)
• mul3 (opcode 35): rc3 = ra3 * rb3 (unsigned)
• mul4 (opcode 36): rc4 = ra4 * rb4 (unsigned)
• mul5 (opcode 37): rc5 = ra5 * rb5 (unsigned)
• mul6 (opcode 38): rc6 = ra6 * rb6 (unsigned)
• mul7 (opcode 39): rc7 = ra7 * rb7 (unsigned)
• mul8 (opcode 40): rc8 = ra8 * rb8 (unsigned)
• smul1 (opcode 41): rc1 = ra1 * rb1 (signed)
• smul2 (opcode 42): rc2 = ra2 * rb2 (signed)
• smul3 (opcode 43): rc3 = ra3 * rb3 (signed)
• smul4 (opcode 44): rc4 = ra4 * rb4 (signed)
• smul5 (opcode 45): rc5 = ra5 * rb5 (signed)
• smul6 (opcode 46): rc6 = ra6 * rb6 (signed)
• smul7 (opcode 47): rc7 = ra7 * rb7 (signed)
• smul8 (opcode 48): rc8 = ra8 * rb8 (signed)
• div1 (opcode 49): rc1 = ra1 / rb1 (unsigned)
• div2 (opcode 50): rc2 = ra2 / rb2 (unsigned)
• div3 (opcode 51): rc3 = ra3 / rb3 (unsigned)
• div4 (opcode 52): rc4 = ra4 / rb4 (unsigned)
• div5 (opcode 53): rc5 = ra5 / rb5 (unsigned)
• div6 (opcode 54): rc6 = ra6 / rb6 (unsigned)
• div7 (opcode 55): rc7 = ra7 / rb7 (unsigned)
• div8 (opcode 56): rc8 = ra8 / rb8 (unsigned)
• sdiv1 (opcode 57): rc1 = ra1 / rb1 (signed)
• sdiv2 (opcode 58): rc2 = ra2 / rb2 (signed)
• sdiv3 (opcode 59): rc3 = ra3 / rb3 (signed)
• sdiv4 (opcode 60): rc4 = ra4 / rb4 (signed)
• sdiv5 (opcode 61): rc5 = ra5 / rb5 (signed)
• sdiv6 (opcode 62): rc6 = ra6 / rb6 (signed)
• sdiv7 (opcode 63): rc7 = ra7 / rb7 (signed)
• sdiv8 (opcode 64): rc8 = ra8 / rb8 (signed)
• mod1 (opcode 65): rc1 = ra1 % rb1 (unsigned)
• mod2 (opcode 66): rc2 = ra2 % rb2 (unsigned)
• mod3 (opcode 67): rc3 = ra3 % rb3 (unsigned)
• mod4 (opcode 68): rc4 = ra4 % rb4 (unsigned)
• mod5 (opcode 69): rc5 = ra5 % rb5 (unsigned)
• mod6 (opcode 70): rc6 = ra6 % rb6 (unsigned)
• mod7 (opcode 71): rc7 = ra7 % rb7 (unsigned)
• mod8 (opcode 72): rc8 = ra8 % rb8 (unsigned)
• smod1 (opcode 73): rc1 = ra1 % rb1 (signed)
• smod2 (opcode 74): rc2 = ra2 % rb2 (signed)
• smod3 (opcode 75): rc3 = ra3 % rb3 (signed)
• smod4 (opcode 76): rc4 = ra4 % rb4 (signed)
• smod5 (opcode 77): rc5 = ra5 % rb5 (signed)
• smod6 (opcode 78): rc6 = ra6 % rb6 (signed)
• smod7 (opcode 79): rc7 = ra7 % rb7 (signed)
• smod8 (opcode 80): rc8 = ra8 % rb8 (signed)

Final Notes

There's more coming, I didn't finish writing this. For example, I couldn't write the stack instructions for now. I also didn't put IO.