Koyaanisqatsi
| Paradigm(s) | imperative |
|---|---|
| Designed by | User:Alikberov |
| Appeared in | 2019 |
| Memory system | flat |
| Dimensions | classic |
| Computational class | Turing complete (Koyaanisqatsi) |
| Reference implementation | Koyaanisqatsi |
| Dialects | Koy-Code, Koy-Code |
| File extension(s) | .koy |
Koyaanisqatsi is an esoteric byte-code paradigm for Virtual Machine with the goal of being simple, what machine code is transparent even for housewife, what was invented in 2019 by User:Alikberov as CPU-Diagram in Logisim program. Lots of byte-code is just abbreviation of instructions and dump just represent the machine code like disassembling view. In this case the machine code coming as pseudocode too.
Conception overview
In present times with lots of different industrial resolves we can looking most human free trends, when programmers become marginalized in self profession, if there needs to go to low level, bypass the compiler, but technology origin want too much knowledge of the architecture, as it was just not designed for manual intervention.
For this reason, for a long time the author considered the task of developing a technology with a friendly intuitive interface starting from the lowest level, like a dump of byte-code.
Yes, this way has its own special undercurrent and strange surprises in unexpected places, which is the price for the specific of the conception.
One of these moments of revelation is the need to introduce subtle esoteric to maintain a balance in functionality, so as not to give rise to coarser esoteric, which can reduce light moments to dry humanless code.
Byte-code overview
It all starts with the fact that conceptually almost everything is called by its proper name at the lowest level of byte-code.
So, codes A1, A2 or A9 means the selection of registers named A1, A2 or A9. In total there are 40 register names related to A B C D blocks 10 in each.
And codes 2D, 3D or 9D means the bitwise Disjunction with registers indexed by 2, 3 and 9. In total there are 6 standard ALU operations: Add suB Con Dis Eor and For.
The codes AB, BC or CD means the combinations of registers blocks in ALU operands field: «A,B», «B,C» or «C,D».
Four codes AF, BF, CF and DF means the complement of flags in PSW (Processor State Word), stored in A0: «Arithmetic Flag», «Biggest Flag», «Carry Flag» and «Difference Flag».
All codes of BCD-range (0116…9916) means the special prefixes for expansion of any instruction or selection processing mode for instruction duration.
Program State Word
| .8 .4 .2 .1 | Logical Pseudonym | x86-Analog | Description |
|---|---|---|---|
| -- -- -- DF | Differential Flag | NZ / JZ | Result is not equal (not 0) |
| -- -- CF -- | Carry Flag | CF / JC | Result is crossed 0 |
| -- BF -- -- | Biggest Flag | OF / JO | Result is overflowed (sign is changed) |
| AF -- -- -- | Arithmetic Flag | SF / JS | Result is negative (is < 0) |
Bits 0 to 3 of register A0 is contains ALU-Flags for conditional branching operations.
Bits 4 to 7 of register A0 is contains current operands section after each ARG-instruction.
Machine Code Samples
| Machine code | Mnemonic | Description |
|---|---|---|
| __ AB __ __ | ARG A,B | Use Operands A,B |
| __ __ A9 __ | REG A9 | Use Register A9 |
| __ __ __ 3D | OR A9,B3 | Bitwise Disjunction A9 and B#3 |
| 12 __ __ 3D | OR A9,[D1+2],B3 | Bitwise Disjunction Memory cell pointed with prefix [D1+2] and B3 then save result to current accumulator (A9) |
| __ __ __ CF | CCF | Complement the CF flag |
| 12 __ __ CF | JCF D1+2 | Jump to address pointed by prefix D1+2 if flag CF is Fictive |
| 12 34 __ CE | JCE D1+D3+24 | Jump to address pointed by prefixes D1+D3+24 if flag CF is Enabled |
| 12 34 56 7C | AND A9,[D1+D3+D5+246],B7 | Bitwise Conjunction Memory cell pointed with prefix [D1+D3+D5+246] and B7 then save result to current accumulator (A9) |
| __ __ __ 00 | HLT | Halt program (Jump to 0 and warm restart BIOS, current IP saving to D0-vector) |
BIOS starting code
Sphinx C-- like dialect
void ReBoot(void) {
// If D0 is clear (this is a "Cold-Start") - then Jump to 256
#pragma org(0)
if( (A9 = B0 | C0) == 0 )
// B0 is alias of D0H - HI(D0)
// C0 is alias of D0L - LO(D0)
IP = 256;
else
// Else there was "Warm-Start" by HALT-command at the address pointed in D0
{
INT(0xF800);
HALT();
}
}
Assembly of BIOS starting code
_IP_ _Byte-Code_ __Short__Record__ _Classic_Record_ _Standard_Record_ ___Descriptions___ 0000 -- AB -- --|A,B |ARG A,B | ;Define Arguments 0001 -- -- A9 --|A9 |REG A9 | ;Select Register 0002 -- -- -- 0F|FOR 0 |FOR A,B0 |MOV A9,B0 ;For A9 load B0 0003 -- AC -- --|A,C |ARG A,C | ;Redefine Arguments 0004 -- -- -- 0D|DIS 0 |OR A,C0 |OR A9,C0 ;Bitwise Disjunction 0005 02 -- -- --|D0+2 |ptr D0+2 | ;Prefixes for ... 0006 -- 05 -- --|D0+2*10+5 |ptr D0+25 | ;...accumulating ... 0007 -- -- 06 --|D0+(2*10+5)*10+6 |ptr D0+256 | ;...pointers for ... 0008 -- -- -- DF|DF |JDF [D0+256] |JZ [D0+256] ;Jump if Zero 0009 -- -- -- F8|F8 |INT F800 |INT [0xF800] ;Interrupt to F80016 000A -- -- -- 00|\0 |HALT |HLT ;After interruption
Few details about Instructions Encoding
ADDR .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F
0000 AB A9 0F AC 0D 02 05 06 DF F8 00 .. .. .. .. ..
/\ /\ /\ /\ /\
|| || || || ||
|| || || || \> Read register #0 in translators section (C0) in "Disjunction" instruction
|| || || ||
|| || || \> Use "C" as right operand (translators now in section "C")
|| || ||
|| || \> Read register #0 in translators section (B0) in "For" instruction
|| ||
|| \> Select in section "A" register #9 as accumulator
||
\> Use "A" as left operand (accumulator) and "B" as right operand (translator)
_IP_ _Byte-Code_ _Standard_Record_ _Analogue_in_C_
0000 -- AB A9 0F|MOV A9,B0 |A9 = B0
0003 -- AC -- 0D|OR A9,C0 |A9 |= C0
0005 02 05 06 DF|JZ [D0+256] |V = D0 + 256; D0 = IP; IP = DFlag ? V : IP
0009 -- -- -- F8|INT [0xF800] |D0 = IP; IP = 0xF800
000A -- -- -- 00|HLT |D0 = IP; IP = 0x0000
000B 90 90 -- 00|HLT9 |Use Extra Mode #9 in Halting
000E 90 90 -- 00|HLT_ |Just syntax feature ('9' is '_')
0011 80 80 -- 00|HLT0 |Just syntax feature ('8' is '0')
Few Extras
_IP_ ____Byte-Code____|_Standard_Assembler_Mnemonic_ _Descriptions_ 7654 -- -- -- DD D0 6A|ADD D0,D6 |D0 += D6 7657 12 -- -- -- -- 6A|ADD D0,D6,[D1+2] |D0 = D6 + *(WORD *)(D1 + 2) 7659 12 34 -- -- -- 6A|ADD D0,D6,#D1+D3+24 |D0 = D6 + *(WORD *)(D1 + D3 + 24) 765C 10 12 34 -- -- 6A|ADD D0,D6,D1+D3-24 |D0 = D6 + *(WORD *)(D1 + D3 - 24) 7660 10 10 -- -- -- 6A|ADD1 D0,D6 |Use Mode #1: is SIMD x86-PADDQ ? 7663 20 20 -- -- -- 6A|ADD2 D0,D6 |Use Mode #2: is SIMD x86-PADDD ? 7666 30 30 -- -- -- 6A|ADD3 D0,D6 |Use Mode #3: is SIMD x86-PADDW ? 7669 40 40 -- -- -- 6A|ADD4 D0,D6 |Use Mode #4: is SIMD x86-PADDB ? 766C 80 80 70 70 -- 6A|ADD87 D0,D6 |Use Mode #87: is i8087-FPU FADD ST(0),ST(6) ? 7671 80 80 70 70 12 6A|ADD D0,87#D1+2,D6 |Use Mode #87: is i8087-FPU FADD DWORD PTR [D1+2] ? 7677 12 34 56 78 90 0F|LEA D0,[D1+D3+D5+D7+D9+24680]|The i8086-Analogue of LEA
Extra Modes
Extra Modes comes like experimental feature with no concretes. That feature become from instructions decoding mechanism and having no strict ideas about using this on this time. One way is using this for co-processing and memory layering, like variant.
External links
- HABR.com Main basical popular description of conception (Anons / Copyleft) with Demo
- AnyCpu.org Forum discussion
- JsFiddle Just live single Instruction Assembly full Encoder