D.E.A.T.H.

D.E.A.T.H.

Paradigm(s)	Imperative, concurrent, adversarial
Designed by	User:Miui
Appeared in	2026
Memory system	Cell-based, shared core
Computational class	Turing complete (in isolation)
Reference implementation	Unimplemented
Influenced by	Redcode
File extension(s)	.death, .red

D.E.A.T.H. (Deadly Embrace At The Hill) is a goto-oriented esoteric programming language by User:Miui in which two programs compete for control of a single simulated processor. It combines the shared-core tournament structure of Core War with Dijkstra's deadly embrace and the IEEE 1788-2015 interval arithmetic standard, using thermal throttling as its damage model.

Overview

Two warriors are loaded into a single chip and execute in alternation. They have no direct attacks: there is no bombing instruction, no self-replication, no imp spiral. The available weapons are uncertainty, which draws power, and mutexes, which are free.

Every value in the language is an IEEE 1788 interval, including the program counter. A core executes every address its PC spans, every cycle, so a wide PC draws proportionally more power. Power raises temperature, temperature triggers throttling, and both cores share one dissipation budget, so cooling is zero-sum.

Either warrior can enter a deadly embrace with the other at any time by acquiring mutexes in opposing order. The machine does not detect deadlock and does not declare a draw. Blocked cores continue to draw power and cannot execute cooling instructions, so a deadlock resolves when the hotter core reaches thermal shutdown and releases its locks. The survivor resumes.

The consequence is that a match is mostly preparation for a deadlock both warriors know is coming, and the deadlock is won by whichever warrior enters it at a lower temperature.

The machine

• One die, two cores, executing in strict alternation (core 0 on even cycles, core 1 on odd).
• Core memory: 8192 cells, addressed mod 8192, shared and writable by both warriors.
• Memory is divided into 64 pages of 128 cells. Each page has a mutex, $0–$63.
• Mutex $64 is the heatsink. It is not backed by memory, but it is acquired and released like any page mutex.
• Warriors are loaded at a random separation of at least 1000 cells. Core 0 moves first.

Cells

Each cell is a 6-tuple:

(opcode, A-mode, A-interval, B-mode, B-interval, decoration)

Uninitialised memory is DAT [0,0] [0,0] decorated trv.

Data model

Intervals

Every operand is a closed interval [lo, hi] over the extended reals. #n denotes the degenerate interval [n, n]. There are no scalar values in the language, including in addresses and in the program counter.

Arithmetic follows IEEE 1788-2015 set-based semantics:

[a,b] + [c,d]  =  [a+c, b+d]
[a,b] × [c,d]  =  [min(ac,ad,bc,bd), max(ac,ad,bc,bd)]
[a,b] ∩ [c,d]  =  ∅  →  NaI

Division by an interval containing zero yields a disjoint pair of intervals. The machine retains both halves rather than taking the hull. See #Decoherence.

Decorations

Each cell carries an IEEE 1788 decoration from the lattice

com  >  dac  >  def  >  trv  >  ill

Decorations propagate by minimum and never increase. This serves as the damage model: a warrior cannot repair its own decorations, only avoid degrading them further.

• Operating on trv data costs double power.
• ill reaching the program counter is an immediate loss.
• MID sets its target's decoration to trv in exchange for collapsing an interval to a point. This makes it the cheap way to recohere, at a permanent cost.

Decoherence

The PC is an interval. Its width w is the number of addresses it spans, and the core executes every instruction in that range on every cycle it is scheduled.

Power drawn on a cycle:

P = base(op) × w × (2 if any operand is trv else 1)

The PC decoheres when:

• POSS branches on a comparison that is neither certainly true nor certainly false. Both targets are taken and both are billed.
• DIV by an interval containing zero writes a disjoint result into it.
• The opponent applies WIDE to it.
• The warrior executes FORK.

The PC recoheres via HULL (constraint narrowing, no decoration cost) or MID (collapse to midpoint, decoration drops to trv).

Temperature sensing

Reading the temperature register T yields

T = [Θ − ε, Θ + ε]   where   ε = (Θ − 20)/8

Sensor error grows with temperature, so a hot core has a poor estimate of how hot it is. As a result, POSS T, #125, panic — a check for imminent shutdown — is unresolvable at exactly the temperatures where it matters, decoheres the PC, and increases power draw. There is no instruction that returns a point temperature.

Thermal model

Let Θᵢ be core i's temperature. Ambient is 20.

Θᵢ ← max(20, Θᵢ + Pᵢ − Dᵢ)

D is the shared dissipation budget, 64 units per cycle for the chip. By default each core receives 32. SINK n transfers n units per cycle from the opponent to the caller; the transfer decays by 1 per cycle toward the default split. SINK requires holding $64.

Threshold	Effect
Θ > 90	Throttled: core executes only every ⌈Θ/90⌉ cycles
Θ > 125	Thermal shutdown, counted as a loss

A throttled core continues to hold its mutexes and continues to accumulate heat from any work it does manage to execute.

Locks and the embrace

• HOLD a — acquire the mutex of the page containing a; blocks if held (Dijkstra's P).
• FREE a — release (V).
• WANT a, b — acquire both mutexes atomically or neither, in the manner of the banker's algorithm.
• SPIN — block voluntarily until lock state changes.

A blocked core dissipates 3 J per cycle and executes no instructions, which means it cannot execute HULL, MID, or IDLE. It holds whatever temperature it had on entering the block and accumulates from there.

When a wait-for cycle forms — for example core 0 holds $17 and wants $64 while core 1 holds $64 and wants $17 — the runtime takes no action. Both cores spin and both heat. The hotter core reaches 125 first, shuts down, and releases its mutexes; the other resumes execution.

WANT is the deadlock-free way to acquire multiple resources, and at 10 J it costs roughly three times a bare HOLD. Correct concurrent code is therefore at a thermal disadvantage against code that acquires locks unsafely.

Instruction set

Syntax is Redcode-like: label MNEM A-operand, B-operand  ; comment

Addressing modes

Mode	Name	Meaning
#	Immediate	The degenerate interval [n,n]
$	Relative	Offset from mid(PC); undefined when w > 1
@	Indirect	Dereference the midpoint of the pointer cell's B-field
%	Midpoint	As @, but collapses the pointer to trv first
*	Spread	The pointer is an interval and addresses every cell it spans; reads take the hull, writes hit all cells and are billed for all of them

Relative addressing is undefined for a decoherent warrior, so decoherence disables most position-independent code until the PC is narrowed.

* scales power with the width of the pointer. * [0,8191] writes the whole core in one instruction at 8192× base cost.

Opcodes

Mnemonic	J	Effect
DAT	—	Data; executing it is a loss
COPY a, b	2	b ← a, decoration = min(dec a, dec b)
ADD SUB MUL	3	IEEE 1788 arithmetic, b ← b ∘ a
DIV a, b	12	If 0 ∈ a, result is disjoint and the target decoheres
HULL a	1	Narrow a by constraint propagation; grants +8 dissipation this cycle
MID a	1	Collapse a to [mid(a), mid(a)]; sets decoration to trv
MEET a, b	4	b ← a ∩ b; if empty, b becomes ill
JOIN a, b	4	b ← hull(a ∪ b)
WIDE a, b	8	Widen b by a in both directions
NAI a	16	Write an ill-decorated cell at a
CERT a, b, L	3	Jump to L if hi(a) < lo(b); never decoheres
POSS a, b, L	3	Jump if lo(a) < hi(b); if undetermined, take both paths
GOTO L	2	Unconditional jump
FORK L	9	PC ← hull(PC ∪ L)
HOLD a	3	Acquire page mutex; blocks
FREE a	1	Release
WANT a, b	10	Acquire both atomically or neither
SPIN	3/cy	Block until lock state changes
SINK a	5	Transfer a dissipation units/cycle from the opponent; requires $64
IDLE a	0	Idle for mid(a) cycles; +4 dissipation/cycle
HALT	0	Surrender

Victory conditions

Checked at the end of every cycle, in order:

1. Thermal shutdown: Θ > 125. Opponent wins.
2. Illness: the PC's decoration reaches ill, or a DAT is executed. Opponent wins.
3. Surrender: HALT.
4. Timeout at 80,000 cycles: the cooler warrior wins on points.
5. Mutual embrace: both cores exceed 125 on the same cycle. Recorded as a loss for both, ranked below a timeout loss.

The Gallery

The losing warrior's core image is passed to slopgen, which generates a replacement listing that becomes its permanent entry on the hill.

The original proposal specified AI-generated pornography. The reference implementation ships a different degradation: the losing warrior is handed to a language model and returned as an enterprise Java refactor, with Hungarian notation, a WarriorStrategyFactoryProvider, a long README explaining what a mutex is, and a generated avatar in corporate-memphis style. The warrior defends its ranking in that form.

Implementations may substitute their own degradation, provided it is generated, permanent, and published.
Nah fam u get turned into AI hentai fuck outta here. Actually it installs GTA6 on everyone's computers and the loser just has to deal with mutant polar bears with guns, which is just a side-effect of losing.

Strategy notes

Three archetypes have stabilised on the reference hill.

Zach

;name     Zach
;strategy Idle at ambient.
loop    HULL   w
        GOTO   loop

Zach never attacks, never acquires a mutex, and never decoheres. Zach sits at ambient for the full 80,000 cycles and wins timeouts under victory condition 4. Beating it requires landing NAI or WIDE, both of which cost the attacker more heat than Zach generates over an entire match. Zach currently holds the hill.

Frostbite

;name     Frostbite
;strategy Enter the embrace at a lower temperature than the opponent.

cool    HULL   w
        HULL   x
        CERT   T, #40, bait      ; certainly under 40
        IDLE   #4
        GOTO   cool

bait    NAI    @lure             ; 16 J, brings us to roughly 45
        HOLD   $64               ; heatsink first
        HOLD   @lure             ; then the page they are executing in
        SPIN                     ; deadlock; we are at 45, they are near 96
        FREE   @lure
        FREE   $64
        GOTO   cool

lure    DAT    #0, [1000, 1400]

The lure cell is bait rather than a weapon: overwriting it costs the opponent 16 J and reading it costs Frostbite 2. Frostbite's weakness is NAI itself, which puts it at around 45° before the deadlock and loses to anything that enters cooler.

Smear

;name     Smear
;strategy Decohere the opponent as widely as possible.
scan    WIDE   #256, *ptr        ; smear a 400-cell window of their PC
        ADD    #400, ptr
        HULL   w
        POSS   T, #90, cool      ; unresolvable above ~80; decoheres us
        GOTO   scan
cool    MID    w                 ; recohere at the cost of trv
        IDLE   #12               ; all subsequent ops now cost double
        GOTO   scan
ptr     DAT    #0, [0, 8191]

Smear self-decoheres every time it checks its own temperature, and its recovery path degrades it to trv, doubling all subsequent power draw. It beats Frostbite and loses to Zach in under 900 cycles.

The general result is that offense is thermally unfavourable: every published weapon costs the attacker more heat than it inflicts on the target. The productive strategy is not to damage the opponent but to arrange conditions in which the opponent chooses to spend heat, which is what Frostbite's lure does.

Computational class

With no opponent loaded, D.E.A.T.H. is Turing complete. Intervals over the extended reals with HULL, MEET and POSS provide unbounded storage and conditional iteration, and IDLE combined with HULL holds a core at ambient indefinitely.

With an opponent loaded, every program halts. Total dissipation is bounded at 64 units per cycle across both cores, every instruction other than HALT and IDLE draws strictly positive power, and decorations decrease monotonically without recovery. The state space is finite and admits a monotone potential function, so both warriors are finite automata on a bounded clock.

Implementation notes

• Do not normalise disjoint division results into their hull; the disjointness drives decoherence.
• Enforce decorations on every write path, including *-mode multi-writes, or the damage model has no effect.
• Compute sensor error ε from the true Θ rather than the reported interval. Otherwise T becomes a fixed point and warriors can iterate to a point estimate.
• The scheduler must not detect or break deadlock, and must not promote blocked cores. Most concurrency runtimes do one or both by default.

See also

• Core War