User:Soundandfury/Ternary ECL

Notes on building a ternary computer using ECL (which for my purposes I'm treating as "summing amplifiers", ie. "analogue weighted sums").

A trith table is like a truth table, but with trits. Trit notation is +,0,- (other common notations are 1,0,A and 1,0,1)

Motivation

• ECL is well-suited to ternary computing, because it can easily represent a (balanced) trit using +V, GND and -V.
• ECL is capable of high performance because all transistors are operating in the linear region. However, this also means that it draws a lot of power and emits a lot of heat. Also, I'm not entirely sure whether my "summing amplifiers" model retains this property.
• The basic units of my model are op-amps and diodes, which are plentiful and cheap, so it should be possible to build prototypes with discrete components (which is just as well, because semiconductor fabs are expensive!).
• I have developed an HDL called ECLAIR, for describing these circuits, as well as simulators for combinatoric and sequential logic circuits written in ECLAIR. As a result, it should be easy to test circuits as they are developed. Eventually it may even be possible to simulate the entire computer.

Half-adder

Trith Table

S	-	0	+
-	+	-	0
0	-	0	+
+	0	+	-

C	-	0	+
-	-	0	0
0	0	0	0
+	0	0	+

Implementation as Circuit

The *-3 and final + amps could be built as one unit (a weighted sum/difference amp). In general however the amps can't all be merged as the saturating behaviour is important. The *-3 actually has to saturate at 3+/3-, which is why it'd be easier to build that gain into the final +.

Implementation in ECLAIR

#NAME Half-adder
#IN A B
#OUT S C
A=INPUT
B=INPUT
CU=SUM - A B
CD=SUM + A B
CUB=DIODE + CU
CDB=DIODE - CD
C=SUM CUB CDB
S=WSUM 1 A 1 B -3 C

Test nonzero

Trith Table

X	NZ
-	+
0	0
+	+

Implementation in ECLAIR

#NAME Nonzero
#IN X
#OUT NZ
X=INPUT
U=DIODE + X
D=DIODE - X
NZ=WSUM 1 U -1 D

By changing the last line to SUM U D, we obtain a 'digitiser'; that is, signals smaller than 0.7V get normalised back to 0 while anything else is amplified up to the full voltage. This is useful in eg. memory, since if we implemented memory the obvious way (MEM=SUM MEM) it would be unstable when storing a 0 (in practice it would immediately diverge to either + or -, randomly).

SR tristable

1-trit memory cell with Set and Reset inputs.

Implementation in #LOOPY ECLAIR

#NAME Memory cell
#IN S R
#OUT D
#LOOPY
S=INPUT
R=INPUT
D=WSUM 2 S 1 Up 1 Dn
DU=DIODE + D
DD=DIODE - D
Up=SUM R DU
Dn=WSUM - R + DD

Swinging S to + or - sets (D<=S), pulling R to + resets (D<=0). Inputs must be held for 3*propagation delay else an ill-defined or oscillating output may result.

/WE Memory Cell

1-trit memory cell with Data and /Write Enable inputs.

Implementation in #LOOPY ECLAIR

#NAME Memory cell (/WE model)
## 1-trit memory using Write Enable model.  Inputs must be held for four clocks.
## WE is active 0.
#IN Din WE
#OUT Dout
#LOOPY
Din=INPUT
WE=INPUT
{
	#NAME NZ
	## Tests nonzero
	#IN X
	#OUT NZ
	X=INPUT
	U=DIODE + X
	D=DIODE - X
	NZ=WSUM + U - D
}
WENZ=NZ WE
WDU=DIODE + Din
WDD=DIODE - Din
WDRU=WSUM 1 WDU 2 WENZ.NZ
WDRD=WSUM -1 WDD 2 WENZ.NZ
WD=WSUM + WDRU - WDRD
Dout=WSUM 1 OD 2 WD
ODU=DIODE + Dout
ODD=DIODE - Dout
ODRU=WSUM 1 ODU 2 + -2 WENZ.NZ
ODRD=WSUM -1 ODD 2 + -2 WENZ.NZ
OD=WSUM + ODRU - ODRD

Inputs must be held for 4*propagation delay.

Note that this is much less efficient than the SR cell above, though perhaps its input semantics make it more useful. If there's any way to save some gates here, I'd like to know it.