TrybblePusher

TrybblePusher is a virtual machine designed (but not yet implemented) by user:viznut in 2014. It is superficially similar to BytePusher but operates on trybbles (3-digit ternary numbers) instead of bytes. Also, instead of static video and audio buffers, it uses a three-processor multiprocessing configuration where processors generate video and audio signals via direct I/O access (see also: Atari 2600).

Rationale

• Since the WordWordJump concept uses three addresses and the optimum seems to be three words per address, ternarity might capture its spirit better than binarity. So, in TrybblePusher, "everything is three".
• WordWordJump machines seem to have some potential as video chips as well as a general-purpose machines, and this potential might be interesting to explore.
• Here's also the chance to try out how oldschool democoding practices scale to the ternary and esoteric spaces. There aren't too many esoteric virtual machines, especially ones that concentrate on audiovisual features.

Processors

Instruction set: TrybbleTrybbleJump, i.e. ternary WordWordJump: 3 addresses per instruction (source address, target address, jump address), 3 trybbles per address, 3 trits per trybble, 3 possible states for trit.

The ternary system is consired balanced (trit values -1, 0 and +1) as in the Soviet Setun computers. The address range is therefore -9841..+9841, and the zero address is at the middle of the memory. The trybble order in all words is big-endian.

The machine has three identical TrybbleTrybbleJump processors designated A, B and C. Their execution is multiplexed on cycle level: during three instruction cycles, each processor gets to execute one instruction.

Initialization:

• Memory image is loaded starting from address 0. After +9841, the address will wrap to -9841. Unloaded memory addresses are filled with zero.
• Processor A starts at address 0, processor B at 9, processor C at 18.

I/O

The i/o space starts from address -14 (the first completely negative memory page) and continues downwards.

Video

Standard tv-style scan, 729x243 pixels per frame, 60 frames per second. The width of each pixel should be about half of its height.

There are nine "global" colors defined by the I/O registers -23..-14. The color space is RGB with one trit per component. R is the most significant trit.

Nine pixels of video signal are generated per three instruction cycles. Thus, each processor gets to execute 81 instructions per scanline, or 1180980 instructions per second.

The color indexes of these nine pixels are formed from registers -27..-24 as follows:

        _____ -24  ____   <- "lores pattern register"
       /               \
       A A A B B B C C C  <- more significant trit
       D E F G H I J K L  <- less significant trit
       \   / \   / \   /
        -27   -26   -25   <- "hires pattern registers"

Processor A is intended by the machine design as the primary video chip, so it jumps back to address zero at start of video frame. (The instruction at 0 is executed just before the color for the first pixel gets calculated.)

Audio

Mono PCM. I/O registers -29 and -28 designate the output voltage.

Input devices

Game controller / cursor keys: (register -40):

• low trit indicates x direction (-1 left, 0 neutral, +1 right)
• middle trit indicates y direction (-1 up, 0 neutral, +1 down)
• high trit indicates trigger direction (0 not pressed)

Keyboard: 27 keys, forming a 9x3 matrix. Each trybble in registers -39..-31 represents a column. There is a state trit for each key: 0 not pressed, +1 pressed, -1 being/just unpressed.

The keyboard also has three potentially useful three-state switches (e.g. letters/trybbles/figures). These are mapped to register -31.

Some emergent features

The trybble-based architecture makes tables relatively compact, so we can manage with the small memory (19863 trybbles ~ 12 KB).

The maximum horizontal resolution of 729 pixels/scanline in 3 colors (or 243 pixels/scanline in 27 colors) can be reached by letting all the processors bang the video registers at the same time. However, if we also want to maintain the maximum vertical resolution, the memory will run out after eight scanlines.

If only one processor does video I/O, the maximum resolution is 243x243 pixels in 3 colors or 81x243 pixels in 27 colors. In this case, another processor needs to be dedicated to updating the source addresses, and the third processor is needed to increment them per scanline. There ought to be enough memory for at least 200 scanlines of framebuffer.

The separation of lores and hires pattern registers makes it possible to experiment with trinary planar effects.