Processor/1
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Processor/1 or P/1 is an esoteric RISC architecture.
Architecture
P/1 is a 64-bit architecture where every register is 64-bit wide. General Purpose Registers are available to the programmer, while special registers are altered by system operation.
Registers
| Quantity | Width | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 256 | 64-bit | General Purpose Registers (GPR) | Available to the programmer. At IPL, value 0x0000000000000000 is affected to register 0 and value 0xFFFFFFFFFFFFFFFF is affected to register 255. | ||||||||||||
| 1 | 64-bit | Program Counter (PC) | Keeps the address of the next instruction to be executed. | ||||||||||||
| 1 | 64-bit | Stack Pointer (SP) | Keeps the address of the top (last element) of the stack. | ||||||||||||
| 1 | 64-bit | Interrupt Pointer (IP) | Keeps the address of the interrupt vector. | ||||||||||||
| 1 | 64-bit | Condition Register (CR) | Keeps flags about the result of arithmetic or comparison instructions.
|
Instructions
Instruction Formats
| Format | Size | Description |
|---|---|---|
| Special | 1 byte | Do not take any operand. |
| Register (R) | 2 bytes | Takes one register as operand. |
| Register, Register(RR) | 3 bytes | Takes two registers as operands. |
| Register, Register, Register (RRR) | 4 bytes | Takes three registers as operands. |
| Register, Immediate (RI) | 10 bytes | Takes one register and one 64-bit immediate value as operands. |
Instruction Set
Special instructions (1 byte)
| Mnemonic | Opcode | Operands | Name | Description |
|---|---|---|---|---|
| NOP | 0xF1 | None | No operation | The PC will be set to the next instruction, but no other operation is performed. |
| RET | 0xF2 | None | Return (stack) | Pop the last word from the stack and branch unconditionally to that address. |
| IL | 0xF3 | None | Interrupt lock | Prevent any interrupt from being executed (used by interrupt handlers). |
| IU | 0xF4 | None | Interrupt unlock | Allow interrupts to be executed (used by interrupt handlers to restore interruption process). |
R instructions (2 byte)
| Mnemonic | Opcode | Operands | Name | Description |
|---|---|---|---|---|
| INT | 0x81 | R | Interrupt | Triggers an interrupt. The register operand contains the interrupt number to be triggered. |
| LPC | 0x82 | R | Load program counter | Loads the PC address into the register operand. |
| LSP | 0x83 | R | Load stack pointer | Loads the SP address into the register operand. |
| LIP | 0x84 | R | Load interrupt vector pointer | Loads the IP address into the register operand. |
| LCR | 0x85 | R | Load condition register | Loads the CR value into the register operand. |
| NOT | 0x86 | R | Not | Invert the value of the register operand (bitwise) |
| PUS | 0x87 | R | Push (stack) | Pushes the register operand value onto the stack. |
| POP | 0x88 | R | Pop (stack) | Pops the value at the top of the stack into the register operand. |
| SIP | 0x89 | R | Set interrupt vector pointer | Sets the IP address to point a new or alternate interrupt vector whose address is the value of the register operand. |
| SSP | 0x8A | R | Set stack pointer | Sets the stack pointer address to the address contained in the register operand. Could be used for context switching. |
| SCR | 0x8B | R | Set condition register | Sets the condition register to the value of the register operand. |
RR instructions (3 byte)
| Mnemonic | Opcode | Operands | Name | Description |
|---|---|---|---|---|
| L | 0x01 | R1,R2 | Load | Loads the value of the second register operand into the first register operand. |
| LS | 0x02 | R1,R2 | Load storage | Loads the 8 bytes at the address contained in the second register operand into the first register operand. |
| ST | 0x03 | R1,R2 | Store | Stores the 8 bytes of the first register operand at the address contained in the second register operand. |
| A | 0x04 | R1,R2 | Add | Adds the second register operand and the first register operand. Stores the result into the first register operand. Handle registers as signed values. |
| AU | 0x05 | R1,R2 | Add unsigned | Adds the second register operand to the first register operand. Stores the result into the first register operand. Handle registers as unsigned values. |
| S | 0x06 | R1,R2 | Substract | Substract the second register operand to the first register operand. Stores the result into the first register operand. Handle registers as signed values. |
| SU | 0x07 | R1,R2 | Substract unsigned | Substract the second register operand to the first register operand. Stores the result into the first register operand. Handle registers as unsigned values. |
| M | 0x08 | R1,R2 | Multiply | Multiply the first register operand by the second register operand. Stores the result into the first register operand. Handle registers as signed values. |
| MU | 0x09 | R1,R2 | Multiply unsigned | Multiply the first register operand by the second register operand. Stores the result into the first register operand. Handle registers as unsigned values. |
| AND | 0x0A | R1,R2 | And | Performs a bitwise AND between the first and second register operands. Stores the result into the first register operand. |
| OR | 0x0B | R1,R2 | Or | Performs a bitwise OR between the first and second register operands. Stores the result into the first register operand. |
| XOR | 0x0C | R1,R2 | Exclusive or | Performs a bitwise XOR between the first and second register operands. Stores the result into the first register operand. |
| B | 0x0D | R1,R2 | Conditional branch | The first register operand is a mask to be applied to the CR. The second register operand contains an address to where to branch if all the bits of the mask matches the Control Register. For example, if R1 contains 00 00 00 00 00 00 00 04, the processor will branch if the last arithmetic operation gave 0 or the last comparison was equal (bit 61 of the Control Register is on). |
| BAS | 0x0E | R1,R2 | Conditional branch and stack | The first register operand is a mask to be applied to the CR. The second register operand contains an address to where to branch if all the bits of the mask matches the Control Register. For example, if R1 contains 00 00 00 00 00 00 00 04, the processor will branch if the last arithmetic operation gave 0 or the last comparison was equal (bit 61 of the Control Register is on). This instruction is similar to Branch, however, the address of the following instruction is stacked before the branch is done (the programmer can then use RET to branch back later). |
| CP | 0x0F | R1,R2 | Compare | Compares the first register operand to the second register operand. Handle registers as signed values. Will update the CR. |
| CPU | 0x10 | R1,R2 | Compare unsigned | Compares the first register operand to the second register operand. Handle registers as unsigned values. Will update the CR. |
| SHL | 0x11 | R1,R2 | Shift left | Shift left the first register operand value the number of time the value of the second register operand isà. |
| SHR | 0x12 | R1,R2 | Shift right | Shift right the first register operand value the number of time the value of the second register operand isà |
RRR instructions (4 byte)
| Mnemonic | Opcode | Operands | Name | Description |
|---|---|---|---|---|
| D | 0xC1 | R1,R2,R3 | Divide | Divides register 1 operand by register 2 operand. Stores the result into the register 1 operand and the remainder into the register 3 operand. Handles registers as signed values. |
| DU | 0xC2 | R1,R2,R3 | Divide unsigned | Divides register 1 operand by register 2 operand. Stores the result into the register 1 operand and the remainder into the register 3 operand. Handles registers as unsigned values. |
| BAL | 0xC3 | R1,R2,R3 | Conditional branch and load | The first register operand is a mask to be applied to the CR. The second register operand contains an address to where to branch if all the bits of the mask matches the Control Register. For example, if R1 contains 00 00 00 00 00 00 00 04, the processor will branch if the last arithmetic operation gave 0 or the last comparison was equal (bit 61 of the Control Register is on). This instruction is similar to Branch, however, the address of the following instruction is stored into the third register operand before the branch is done (the programmer can then use it to branch back later). |
| LSM | 0xC4 | R1,R2,R3 | Load storage multiple | First and second register operands contain register numbers (between 0 and 255, inclusive). Third register operand contains the address where all the register of the interval specified by first and second register operands are to be loaded from. For example, if the first register operand contains 3 and second register operand 7, registers 3, 4, 5, 6 and 7 will be sequentially loaded from the address contained in the third operand. |
| STM | 0xC5 | R1,R2,R3 | Store multiple | First and second register operands contain register numbers (between 0 and 255, inclusive). Third register operand contains the address where all the register of the interval specified by first and second register operands are to be stored. For example, if the first register operand contains 3 and second register operand 7, registers 3, 4, 5, 6 and 7 will be sequentially stored at the address contained in the third operand. |
| LUM | 0xC6 | R1,R2,R3 | Load under mask | First register operand is a mask specifying which bytes of second register operand are to be loaded from the address contained in the third register operand. For example, if the first register operand contains 00 00 00 00 00 FF FF FF FF, only the four lower bytes of the second register operand will be loaded from the 4 first bytes at the address contained in the third register operand. |
| SUM | 0xC7 | R1,R2,R3 | Store under mask | First register operand is a mask specifying which bytes of second register operand are to be stored at the address contained in the third register operand. For example, if the first register operand contains 00 00 00 00 00 FF FF FF FF, only the four lower bytes of the second register operand will be stored to the 4 first bytes at the address contained in the third register operand. |
RI instructions (10 byte)
| Mnemonic | Opcode | Operands | Name | Description |
|---|---|---|---|---|
| LI | 0xE1 | R,I | Load immediate | Loads the immediate value operand into the register operand. The immediate value is 64-bit wide. |
Implementations
As of 2007, only one software implementation exists of the P/1 architecture exists (a crude virtual machine developed in .Net). There is no hardware implementation yet.
As of 2016, a new software implementation exists (unstable).
XASM: Processor/1 Cross Assembler (requires .Net framework) (dead link)
XASM: Processor/1 Machine (requires .Net framework) (dead link)
P/1 implementation in C (With a little assembler written in Python)