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Mecrisp-Ternary
Mecrisp-Ternary is an experiment to explore Forth on a custom variable-width, word-addressed, balanced ternary stack machine architecture. The look and feel is mostly aligned with Forth, with logic operators unique to ternary machines added, and the language carefully enhanced to accommodate the existence of three well formed flags. An instruction set emulator in C is provided along with Verilog sources, so you can run Mecrisp-Ternary on your desktop machine, in Verilator, or on the ULX3S and Icebreaker FPGA boards.
Special features include:
- Variable width, starting from a minimum of 10 trits due to the instruction set design and no maximum, with implementations provided out of the box for 10, 12 and 27 trits. The Forth nucleus containing the compiler is carefully written in a width-agnostic way, and running it in simulation, it can compile the rest of the source code, applying constant folding and tail-call optimisations for the width you desired.
- Real implementations on FPGAs, running at reasonable clock frequencies. The logic of Mecrisp-Ternary is written in standard Verilog, so if you want to get started in using balanced ternary on natively binary FPGAs, enjoy!
- Interrupts, cooperative multitasking, fixpoint calculations, gray codes...