Braindumbed

Braindumbed is esoteric instruction set architecture designed by User:Filexor.

Language overview

Braindumbed generally runs with 65536 bits of address space with memory mapped I/O. Braindumbed has following registers:

name	meaning	description
C	Compute	1 bit long register.
D	Data	A register indexed by I. Generally 16 bits long.
I	Index	A register used for indexing D. Can represent any position of D (and so generally 4 bits long).
A	Address	A register for specifying memory address. Has same length as D.
P	Program Counter	A program counter points next address of instruction. Has same length as D.

Braindumbed has following instructions:

symbol	code	operation	Description
a	001	C=!(C&D[I])	D[I] is I-th bit of D (Starts from 0).
b	010	I++
c	011	T=D;D=A;A=T	T is temporal register.
d	100	if(C==0){T=A;A=P;P=T}	T is temporal register.
e	101	C=$A	$A is a memory where A specifies.
f	110	$A=C	$A is a memory where A specifies.
g	000	NOP	NOP does nothing.
h	111	D[I]=C	D[I] is I-th bit of D (Starts from 0).

Examples

Note: These codes destroy part of D.

NOT

ha

Load 1 to C

haa

Load 0 to C

haaha

From following, b(n) represents repeat b n-times. And I represents initial state of I.

Move D[I] to C

D[J] will be destroyed.

b(J-I)haab(I-J)ab(J-I)ha

AND

D[J] will be destroyed.

ab(J-I)ha

OR

D[J] and D[K] will be destroyed.

b(J-I)hah
b(K-J)haab(I-K)ab(K-I)ha
b(I-K)ab(J-I)a

Half-adder or XOR

D[K] and D[L] will be destroyed. D[M]=D[I]&D[J] (carry)

b(K-I)haab(I-K)ab(K-I)ha
b(J-K)ab(K-J)h
b(I-K)ab(L-I)h
b(M-L)haab(K-M)ab(M-K)ha
b(J-M)ab(L-J)a

Usability

Because of code inefficiently (Just loading 16-bit data take more than 30720-bit of ROM), with default configuration, this ISA can be considered as unusable for programming. However, with larger register size, this ISA may be usable for programming (need verification).