Talk:Word!CPU

RISC or what? Here we go: I've designed a RISC processor with a 40-bit (5-byte) instruction length (it's a 16-bit processor, an 8-bit version would have 24-bit / 3-byte instructions but need a 16-bit PC, which would be irritating D:): a byte for the instruction opcode (xyzzzzzz: x=declare field A as pointer, y=declare field B as pointer, z=opcode) and two 2-byte fields. But some of the instructions would only use the first field, so you could store a command in the second field, and jump into that. It would do all main operations in memory, which is why it has a cache.
 * Each instruction has a fixed length.
 * Main instructions are either done entirely in memory or entirely in registers. This suits the former.

That's actually quite a nice-looking CPU there ;D. Perhaps you could have some special modes? --GreaseMonkey 23:05, 26 Nov 2006 (UTC)
 * What special modes do you mean? I could add some, if I know what to add. (well, maybe...) --Zzo38 23:46, 26 Nov 2006 (UTC)