Pendulum Instruction Set Architecture

Pendulum Instruction Set Architecture (PISA) is a reversible instruction set architecture. It resembles a cross between standard RISC and PDP-8 with modifications to support reversibility.

Introduction
This section quotes from [1] (Vieri95).


 * Memory access is always an exchange. To copy a value, ensure that one register is clear (by exchanging it with an empty memory location if necessary) and add the other register to it in  where   is originally clear.


 * Control flow operations must appear in identical pairs.

Example
Fibonacci example copied from [1] (Vieri95).

Add
Format:

Description: The contents of register rsd and register rt are added to form a 12-bit result. The result is placed in register rsd.

Operation:

Add Immediate
Format:

Description: The 9-bit immediate is sign extended and added to the contents of register rsd. The result is placed in register rsd.

Operation:

And Immediate
Format:

Description: The 9-bit immediate is sign extended and combined with the contents of register rs in a bit-wise logical AND operation. The result is combined in a logical XOR with the contents of register rd and is placed in register rd.

Operation:

And-Xor
Format:

Description: The contents of register rs and register rt are combined in a bit-wise logical AND operation. The result is combined in a logical XOR with the contents of register rd and is placed in register rd.

Operation:

Branch On Equal to Zero
Format:

Description: The contents of register rb are compared to zero. If the contents of the register equal zero, the program branches to the address specified in register ra by exchanging the contents of ra with the value of the program counter.

Operation:

Branch On Less Than Zero
Format:

Description: If the contents of register rb have the sign bit set the program branches to the address specified in register ra by exchanging the contents of ra with the value of the program counter.

Operation:

Exchange
Format:

Description: The contents of register exch are placed at the data memory location specified by the contents of register ''addr'. The contents of the data memory location specified by the contents of register addr are placed in register exch.

Operation:

Or Immediate-Xor
Format:

Description: The 9-bit immediate is sign extended and combined with the contents of register rs in a bit-wise logical OR operation. The result is combined in a logical XOR with the contents of register rd and is placed in register rd.

Operation:

Or Xor
Format:

Description: The contents of register rs and register rt are combined in a bit-wise logical OR operation. The result is combined in a logical XOR with the contents of register rd and is placed in register rd.

Operation:

Reverse Direction, Branch On Equal to Zero
Format:

Description: The contents of register rb are compared to zero. If the contents of the register equal zero, the program branches to the address specified in register ra by exchanging the contents of ra with the value of the program counter. The global direction bit is also toggled when this instruction is executed.

Operation:

Reverse Direction, Branch On Less Than Zero
Format:

Description: If the contents of register rb have the sign bit set the program branches to the address specified in register ra by exchanging the contents of ra with the value of the program counter. The global direction bit is also toggled when this instruction is executed.

Operation:

Rotate Left
Format:

Description: The contents of register rsd are rotated left one bit. The result is placed in register rsd.

Operation:

Rotate Right
Format:

Description: The contents of register rsd are rotated right one bit. The result is placed in register rsd.

Operation:

Shift Left Logical-Xor
Format:

Description: The contents of register rs are shifted left by one bit, inserting zero into the lower order bit. The result is combined in a logical XOR with the contents of register rd and is placed in register rd.

Operation:

Shift Right Arithmetic-Xor
Format:

Description: The contents of register rs are shifted right by one bit, sign extending the high order bit. The result is combined in a logical XOR with the contents of register rd and is placed in register rd.

Operation:

Exclusive Or
Format:

Description: The contents of register rsd and register ''rs' are combined in a bit-wise logical exclusive OR operation. The result is placed in register rsd.

Operation:

Xor Immediate
Format:

Description: The 9-bit immediate is sign extended and combined with the contents of register rsd in a bit-wise logical XOR operation. The result is placed in register rsd.

Operation:

External resources

 * PISA Assembler
 * An Introduction to Reversible Computing Using PhPISA - Includes a tutorial PDF
 * Pendulum VM simulator