User:Feuermonster/ILIPU

Insanely Large Instruction Set Processing Unit is a new esoteric CPU project of mine. The idea is to achieve a huge amount of instructions. An Instruction has a 15bit opcode or a 7bit opcode and 8bit immediate data. The goal is to make it incredibly hard to write programs in assembler language in it and incredibly hard to write a Compiler for it.

Current Instruction Listing
NUM	OPCODE	DESCRIPTION LDCQ	Load Constant To Q	LDCR	... LDCS	... LDCT	... LDCU	... LDCV	... LDCA	Load Constant To REGS[OPA] LDCB 	Load Constant To REGS[OPB] 0000	OPAQ	Set Operand A to Q 0000	OPAR	Set Operand A to R 0000	OPAS	... 0000	OPAT	... 0000	OPAU	... 0000	OPAV	... 0000	OPBQ	Set Operand B to Q 0000	OPBR	Set Operand B to R 0000	OPBS	... 0000	OPBT	... 0000	OPBU	... 0000	OPBV	... 0000	INCA	Increment (OPA) 0000	INCB	Increment (OPB) 0000	DECA	Decrement (OPA) 0000	DECB	Decrement (OPB) 0000	INCX	Increment (OPA and OPB) 0000	DECX	Decrement (OPA and OPB) 0000	LINC	Load and Increment (REGS[OPA] = (MEM[REGS[OPB]]) + 1) 0000	LDEC	Load and Decrement (REGS[OPA] = (MEM[REGS[OPB]]) - 1) 0000	LOAD	Load (REGS[OPA] = MEM[REGS[OPB]]) 0000	SLDA	Single Load A (REGS[OPA] = MEM[REGS[OPA]]) 0000	SLDB	Single Load B (REGS[OPB] = MEM[REGS[OPB]]) 0000	DBLD	Double Load (REGS[OPA] = MEM[REGS[OPA]] AND REGS[OPB] = MEM[REGS[OPB]]) 0000	DXLD	Double Load Crossed (REGS[OPA] = MEM[REGS[OPB]] AND REGS[OPB] = MEM[REGS[OPA]]) 0000	LDIN	Load Indirect (REGS[OPA] = MEM[MEM[REGS[OPB]]]) 0000	LDDI	Load Double Indirect (REGS[OPA] = MEM[MEM[MEM[REGS[OPB]]]]) 0000	STOR	Store (MEM[REGS[OPB]] = REGS[OPA]) 0000	STIN	Store Indirect (MEM[MEM[REGS[OPB]]] = REGS[OPA]) 0000	STDI	Store Double Indirect (MEM[MEM[MEM[REGS[OPB]]]] = REGS[OPA]) 0000	SINC	Store and Increment (MEM[REGS[OPB]] = REGS[OPA] AFTERWARDS REGS[OPA]++) 0000	SDEC	Store and Decrement (MEM[REGS[OPB]] = REGS[OPA] AFTERWARDS REGS[OPA]--) 0000	LDST	Load and Store (REGS[OPA] = MEM[REGS[OPB]] AND MEM[REGS[OPB]] = REGS[OPA]) 0000	LDOF	Load With Offset (REGS[OPA] = MEM[REGS[OPB] + REGS[V]]) 0000	STOF	Store With Offset (MEM[REGS[OPB] + REGS[V]] = REGS[OPA) 0000	SETV	Set V Register (REGS[V] = REGS[OPA]) 0000	GETV	Get V Register (REGS[OPA] = REGS[V]) 0000	LDVA	Load V With A (REGS[V] = MEM[REGS[OPA]) 0000	LDVB	Load V with B (REGS[V] = MEM[REGS[OPB]] 0000	STVA	Store V With A (MEM[REGS[OPA]] = REGS[V]) 0000	STVB	Store V with B (MEM[REGS[OPB]] = REGS[V]) 0000	STBY	Store Byte (Lowest) (BYTE MEM[REGS[OPB]] = REGS[OPA] & 0xffu) 0000	LDBY	Load Byte (To Lowest) (BYTE REGS[OPA] = MEM[REGS[OPB]]) 0000	BRHA	Unconditional Branch (PC = REGS[OPA]) 0000	BRHB	Unconditional Branch (PC = REGS[OPB]) 0000	BRHM	Unconditional Branch (PC = MEM[REGS[OPB]]) 0000	BREQ	Branch If Equal (PC = REGS[V] IF REGS[OPA] == REGS[OPB]) 0000	BRNE	Branch If Not Equal (PC = REGS[V] IF REGS[OPA] != REGS[OPB]) 0000	BIZM	Branch With Increment From Memory If Zero (REGS[OPA] += 1 AFTERWARDS PC = V IF MEM[REGS[OPA]] == 0) 0000	BINM	Branch With Increment From Memory If Not Zero (REGS[OPA] += 1 AFTERWARDS PC = V IF MEM[REGS[OPA]] == 0) 0000	ADDA	Add Result In A (REGS[OPA] += REGS[OPB]) 0000	ADDB	Add Result in B (REGS[OPB] += REGS[OPA]) 0000	ADFM	Add From Memory (REGS[OPA] += MEM[REGS[OPB]]) 0000	ADTM	Add To Memory (MEM[REGS[OPB]] += REGS[OPA]) 0000	ADMM	Add Memory To Memory (MEM[REGS[OPA]] += MEM[REGS[OPB]]) 0000	ADMU	Add And Multiply Unsigned (REGS[OPA] = (REGS[OPA] + REGS[OPB]) * REGS[OPB]) 0000	ADDU	Add And Divide Unsigned (REGS[OPA] = (REGS[OPA] + REGS[OPB]) / REGS[OPB]) 0000	ADMS	Add and Multiply Signed (REGS[OPA] = (REGS[OPA] + REGS[OPB]) * REGS[OPB]) 0000	ADDS	Add And Divide Signed (REGS[OPA] = (REGS[OPA] + REGS[OPB]) / REGS[OPB]) 0000	SHLF	Shift Left (REGS[OPA] <<= REGS[OPB]) 0000	SHLM	Shift Left In Memory (MEM[REGS[OPA]] <<= REGS[OPB]) 0000	SHRT	Shift Right (REGS[OPA] >>= REGS[OPB]) 0000	SHRM	Shift Right In Memory (MEM[REGS[OPA]] >>= REGS[OPB]) 0000	SLMM	Shift Left Both In Memory (MEM[REGS[OPA]] <<= MEM[REGS[OPB]]) 0000	SRMM	Shift Right Both In Memory (MEM[REGS[OPA]] >>= MEM[REGS[OPB]]) 0000	NOTA	Bitwise Not A (REGS[OPA] = ~REGS[OPA]) 0000	NOTB	Bitwise Not B (REGS[OPB] = ~REGS[OPB]) 0000	NOTX	Bitwise Not (REGS[OPA] = ~REGS[OPB]) 0000	NOTM	Bitwise Not In Memory (MEM[REGS[OPA]] = ~MEM[REGS[OPA]]) 0000	OR__	Bitwise Or (REGS[OPA] |= REGS[OPB]) 0000	ORM_	Bitwise Or In Memory (MEM[REGS[OPA]] |= REGS[OPB]) 0000	AND_	Bitwise And (REGS[OPA] &= REGS[OPB]) 0000	ANDM	Bitwise And In Memory (MEM[REGS[OPA]] &= REGS[OPB]) 0000	XOR_	Bitwise Xor (REGS[OPA] ^= REGS[OPB]) 0000	XORM	Bitwise Xor In Memory (MEM[REGS[OPA]] ^= REGS[OPA]) 0000	NOR_	Bitwise Nor (REGS[OPA] = ~(REGS[OPA] | REGS[OPB]) 0000	NAND	Bitwise NAND (REGS[OPA] = ~(REGS[OPA] & REGS[OPB]) 0000	XNOR	Bitwise XNOR (REGS[OPA] = ~(REGS[OPA] ^ REGS[OPB]) 0000	SET_	Set (REGS[OPA] = REGS[OPB]) 0000	GET_	Get (REGS[OPB] = REGS[OPA]) 0000	SWAB	Swap A/B (OPA, OPB = OPB, OPA) 0000	SBIT	Set Bit (Set Bit REGS[OPB] in REGS[OPA]) 0000	SBTM	Set Bit In Memory (Set Bit REGS[OPB] in MEM[REGS[OPA]]) 0000	UBIT	Unset Bit (Unset Bit REGS[OPB] in REGS[OPA]) 0000	UBTM	Unset Bit in Memory (Unset Bit REGS[OPB] in MEM[REGS[OPA]]) 0000	XCHG	Exchange Registers (REGS[OPA], REGS[OPB] = REGS[OPA]) 0000	SWAP	Swap In Memory (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]]) 0000	LOG2	Integer Log 2 (Calculate Log 2 of REGS[OPA]) 0000	FBCD	From BCD (REGS[OPA] = FROMBCD(REGS[OPB])) 0000	TBCD	To BCD (REGS[OPB] = TOBCD(REGS[OPA])) 0000	OUTM	Out From Memory (putc(MEM[REGS[OPA]]) 0000	OUTA	Out (putc[REGS[OPA]]) 0000	OUTB	Out (putc[REGS[OPB]]) 0000	OUTS	Out String (ptr in REGS[OPA] to zero terminated string -> print to stdout) 0000	INM_	In To Memory (MEM[REGS[OPA]] = getc(stdin)) 0000	INA_	In (REGS[OPA] = getc(stdin)) 0000	INB_	In (REGS[OPB] = getc(stdin)) 0000	INS_	In String (REGS[OPA] points to a buffer) 0000	INSS	In String (REGS[OPA] points to a buffer, REGS[OPB] how many bytes to read) 0000	SWIE	Swap If Equal (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF MEM[REGS[OPA]] == MEM[REGS[OPB]]) 0000	SWNE	Swap If Not Equal (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF MEM[REGS[OPA]] != MEM[REGS[OPB]]) 0000	SWIL	Swap If Less (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF SIGNED MEM[REGS[OPA]] < MEM[REGS[OPB]]) 0000	SWIG	Swap If Greater (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF SIGNED MEM[REGS[OPA]] > MEM[REGS[OPB]]) 0000	SWLE	Swap If Less Or Equal (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF SIGNED MEM[REGS[OPA]] <= MEM[REGS[OPB]]) 0000	SWGE	Swap If Greater Or Equal (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF SIGNED MEM[REGS[OPA]] >= MEM[REGS[OPB]]) 0000	SWIB	Swap If Below (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF MEM[REGS[OPA]] < MEM[REGS[OPB]]) 0000	SWIA	Swap If Above (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF MEM[REGS[OPA]] > MEM[REGS[OPB]]) 0000	SWBE	Swap If Below Or Equal (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF MEM[REGS[OPA]] <= MEM[REGS[OPB]]) 0000	SWAE	Swap If Above Or Equal (MEM[REGS[OPA]], MEM[REGS[OPB]] = MEM[REGS[OPB]], MEM[REGS[OPA]] IF MEM[REGS[OPA]] >= MEM[REGS[OPB]]) 0000	SWBN	Swap And Branch If Not Equal (MEM[REGS[OPA]], MEM[REGS[OPA]] = MEM[REGS[OPB]], MEM[REGS[OPA]] AFTERWARDS PC = REGS[V] IF REGS[OPA] != REGS[OPB]) 0000	IRIN	Increment Repeat If Not Zero (REGS[OPA] += 1 AND REGS[OPB] += 1 REPEAT INSTRUCTION UNTIL MEM[REGS[OPA]] == 0)